arm64: dts: hisi: add refclk node to hip06 dts files for SAS (85f5bd9e) · Commits · 戴 / test

We will only maintain 1 dts for D03 and there are 50MHz and 66MHz versions of D03: so we expect UEFI to update refclk rate in the fdt at boot time. Signed-off-by:

John Garry <john.garry@huawei.com> Reviewed-by:

Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by:

Wei Xu <xuwei5@hisilicon.com>

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+9 −0

Original line number	Diff line number	Diff line
		@@ -318,6 +318,12 @@
		#size-cells = <2>;
		ranges;

		refclk: refclk {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		#clock-cells = <0>;
		};

		usb_ohci: ohci@a7030000 {
		compatible = "generic-ohci";
		reg = <0x0 0xa7030000 0x0 0x10000>;
		@@ -552,6 +558,7 @@
		ctrl-reset-reg = <0xa60>;
		ctrl-reset-sts-reg = <0x5a30>;
		ctrl-clock-ena-reg = <0x338>;
		clocks = <&refclk 0>;
		queue-count = <16>;
		phy-count = <8>;
		dma-coherent;
		@@ -594,6 +601,7 @@
		ctrl-reset-reg = <0xa18>;
		ctrl-reset-sts-reg = <0x5a0c>;
		ctrl-clock-ena-reg = <0x318>;
		clocks = <&refclk 0>;
		queue-count = <16>;
		phy-count = <8>;
		dma-coherent;
		@@ -635,6 +643,7 @@
		ctrl-reset-reg = <0xae0>;
		ctrl-reset-sts-reg = <0x5a70>;
		ctrl-clock-ena-reg = <0x3a8>;
		clocks = <&refclk 0>;
		queue-count = <16>;
		phy-count = <9>;
		dma-coherent;

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