Commit 85d13c00 authored by Will Deacon's avatar Will Deacon
Browse files

arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003 



The pre_ttbr0_update_workaround hook is called prior to context-switching
TTBR0 because Falkor erratum E1003 can cause TLB allocation with the wrong
ASID if both the ASID and the base address of the TTBR are updated at
the same time.

With the ASID sitting safely in TTBR1, we no longer update things
atomically, so we can remove the pre_ttbr0_update_workaround macro as
it's no longer required. The erratum infrastructure and documentation
is left around for #E1003, as it will be required by the entry
trampoline code in a future patch.

Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Tested-by: default avatarLaura Abbott <labbott@redhat.com>
Tested-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 7655abb9

arch/arm64/include/asm/assembler.h

+0 −22
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/debug-monitors.h>

#include <asm/mmu_context.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>
@@ -478,27 +477,6 @@ alternative_endif 
	.endm



/*

 * Errata workaround prior to TTBR0_EL1 update

 *

 * 	val:	TTBR value with new BADDR, preserved

 * 	tmp0:	temporary register, clobbered

 * 	tmp1:	other temporary register, clobbered

 */

	.macro	pre_ttbr0_update_workaround, val, tmp0, tmp1

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003

	mrs	\tmp0, ttbr0_el1

	mov	\tmp1, #FALKOR_RESERVED_ASID

	bfi	\tmp0, \tmp1, #48, #16		// reserved ASID + old BADDR

	msr	ttbr0_el1, \tmp0

	isb

	bfi	\tmp0, \val, #0, #48		// reserved ASID + new BADDR

	msr	ttbr0_el1, \tmp0

	isb

alternative_else_nop_endif

#endif

	.endm



/*

 * Errata workaround post TTBR0_EL1 update.

 */

arch/arm64/include/asm/mmu_context.h

+0 −2
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ 
#ifndef __ASM_MMU_CONTEXT_H

#define __ASM_MMU_CONTEXT_H



#define FALKOR_RESERVED_ASID	1



#ifndef __ASSEMBLY__



#include <linux/compiler.h>

arch/arm64/mm/context.c

+0 −11
Original line number Diff line number Diff line
@@ -79,13 +79,6 @@ void verify_cpu_asid_bits(void) 
	}

}



static void set_reserved_asid_bits(void)

{

	if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&

	    cpus_have_const_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))

		__set_bit(FALKOR_RESERVED_ASID, asid_map);

}



static void flush_context(unsigned int cpu)

{

	int i;
@@ -94,8 +87,6 @@ static void flush_context(unsigned int cpu) 
	/* Update the list of reserved ASIDs and the ASID bitmap. */

	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);



	set_reserved_asid_bits();



	for_each_possible_cpu(i) {

		asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);

		/*
@@ -254,8 +245,6 @@ static int asids_init(void) 
		panic("Failed to allocate bitmap for %lu ASIDs\n",

		      NUM_USER_ASIDS);



	set_reserved_asid_bits();



	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);

	return 0;

}

arch/arm64/mm/proc.S

+0 −1
Original line number Diff line number Diff line
@@ -138,7 +138,6 @@ ENDPROC(cpu_do_resume) 
 *	- pgd_phys - physical address of new TTB

 */

ENTRY(cpu_do_switch_mm)

	pre_ttbr0_update_workaround x0, x2, x3

	mrs	x2, ttbr1_el1

	mmid	x1, x1				// get mm->context.id

	bfi	x2, x1, #48, #16		// set the ASID

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