Commit 85b0cae8 authored Jan 31, 2019 by Mika Westerberg Committed by Bjorn Helgaas Feb 11, 2019

PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports

Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is
connected to an Alpine Ridge Thunderbolt controller.  This port has slot
implemented bit set in the config space but other than that it is not
hotplug capable in the sense we are expecting in Linux (it has
dev->is_hotplug_bridge set to 0):

  00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5
    Bus: primary=00, secondary=05, subordinate=46, sec-latency=0
    Memory behind bridge: 78000000-8fffffff [size=384M]
    Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M]
    ...
    Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
    ...
      SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
	      Slot #8, PowerLimit 25.000W; Interlock- NoCompl+
      SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
	      Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
      SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
	      Changed: MRL- PresDet+ LinkState+

This system is using ACPI based hotplug to notify the OS that it needs to
rescan the PCI bus (ACPI hotplug).

If there is nothing connected in any of the Thunderbolt ports the root port
will not have any runtime PM active children and is thus automatically
runtime suspended pretty soon after boot by PCI PM core.  Now, when a
device is connected the BIOS SMI handler responsible for enumerating newly
added devices is not able to find anything because the port is in D3.

Prevent this from happening by blacklisting PCI power management of this
particular Gigabyte system.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=202031


Reported-by: Kedar A Dongre <kedar.a.dongre@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

parent bfeffd15

drivers/pci/pci.c

+22 −0

Original line number	Diff line number	Diff line
		@@ -2501,6 +2501,25 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev)
		pm_runtime_put_sync(parent);
		}

		static const struct dmi_system_id bridge_d3_blacklist[] = {
		#ifdef CONFIG_X86
		{
		/*
		* Gigabyte X299 root port is not marked as hotplug capable
		* which allows Linux to power manage it. However, this
		* confuses the BIOS SMI handler so don't power manage root
		* ports on that system.
		*/
		.ident = "X299 DESIGNARE EX-CF",
		.matches = {
		DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
		DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
		},
		},
		#endif
		{ }
		};

		/**
		* pci_bridge_d3_possible - Is it possible to put the bridge into D3
		* @bridge: Bridge to check
		@@ -2546,6 +2565,9 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
		if (bridge->is_hotplug_bridge)
		return false;

		if (dmi_check_system(bridge_d3_blacklist))
		return false;

		/*
		* It should be safe to put PCIe ports from 2015 or newer
		* to D3.

Admin message