MIPS: ralink: adds include files

/*

 *  Ralink SoC register definitions

 *

 *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>

 *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>

 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 */

#ifndef _RALINK_REGS_H_

#define _RALINK_REGS_H_

extern __iomem void *rt_sysc_membase;

extern __iomem void *rt_memc_membase;

static inline void rt_sysc_w32(u32 val, unsigned reg)

{

	__raw_writel(val, rt_sysc_membase + reg);

}

static inline u32 rt_sysc_r32(unsigned reg)

{

	return __raw_readl(rt_sysc_membase + reg);

}

static inline void rt_memc_w32(u32 val, unsigned reg)

{

	__raw_writel(val, rt_memc_membase + reg);

}

static inline u32 rt_memc_r32(unsigned reg)

{

	return __raw_readl(rt_memc_membase + reg);

}

#endif /* _RALINK_REGS_H_ */

/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>

 */

#ifndef __ASM_MACH_RALINK_WAR_H

#define __ASM_MACH_RALINK_WAR_H

#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define RM9000_CDEX_SMP_WAR		0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

#endif /* __ASM_MACH_RALINK_WAR_H */

/*

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 *

 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>

 */

#ifndef _RALINK_COMMON_H__

#define _RALINK_COMMON_H__

#define RAMIPS_SYS_TYPE_LEN	32

struct ralink_pinmux_grp {

	const char *name;

	u32 mask;

	int gpio_first;

	int gpio_last;

};

struct ralink_pinmux {

	struct ralink_pinmux_grp *mode;

	struct ralink_pinmux_grp *uart;

	int uart_shift;

	void (*wdt_reset)(void);

};

extern struct ralink_pinmux gpio_pinmux;

struct ralink_soc_info {

	unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];

	unsigned char *compatible;

};

extern struct ralink_soc_info soc_info;

extern void ralink_of_remap(void);

extern void ralink_clk_init(void);

extern void ralink_clk_add(const char *dev, unsigned long rate);

extern void prom_soc_init(struct ralink_soc_info *soc_info);

__iomem void *plat_of_remap_node(const char *node);

#endif /* _RALINK_COMMON_H__ */