Commit 855cdfde authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by David S. Miller
Browse files

net: dsa: mv88e6xxx: implement watchdog_ops for mv88e6250 



The MV88E6352_G2_WDOG_CTL_* bits almost, but not quite, describe the
watchdog control register on the mv88e6250. Among those actually
referenced in the code, only QC_ENABLE differs (bit 6 rather than bit
5).

Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarVivien Didelot <vivien.didelot@gmail.com>
Signed-off-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bec8e572

drivers/net/dsa/mv88e6xxx/global2.c

+26 −0
Original line number Diff line number Diff line
@@ -816,6 +816,32 @@ const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = { 
	.irq_free = mv88e6097_watchdog_free,

};



static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip)

{

	u16 reg;



	mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, &reg);



	reg &= ~(MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE |

		 MV88E6250_G2_WDOG_CTL_QC_ENABLE);



	mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg);

}



static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip)

{

	return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL,

				  MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE |

				  MV88E6250_G2_WDOG_CTL_QC_ENABLE |

				  MV88E6250_G2_WDOG_CTL_SWRESET);

}



const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {

	.irq_action = mv88e6097_watchdog_action,

	.irq_setup = mv88e6250_watchdog_setup,

	.irq_free = mv88e6250_watchdog_free,

};



static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)

{

	return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,

drivers/net/dsa/mv88e6xxx/global2.h

+14 −0
Original line number Diff line number Diff line
@@ -205,6 +205,18 @@ 
#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK	0x7f00

#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK	0x00ff



/* Offset 0x1B: Watch Dog Control Register */

#define MV88E6250_G2_WDOG_CTL			0x1b

#define MV88E6250_G2_WDOG_CTL_QC_HISTORY	0x0100

#define MV88E6250_G2_WDOG_CTL_QC_EVENT		0x0080

#define MV88E6250_G2_WDOG_CTL_QC_ENABLE		0x0040

#define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY	0x0020

#define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT	0x0010

#define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE	0x0008

#define MV88E6250_G2_WDOG_CTL_FORCE_IRQ		0x0004

#define MV88E6250_G2_WDOG_CTL_HISTORY		0x0002

#define MV88E6250_G2_WDOG_CTL_SWRESET		0x0001



/* Offset 0x1B: Watch Dog Control Register */

#define MV88E6352_G2_WDOG_CTL			0x1b

#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT	0x0080
@@ -334,6 +346,7 @@ int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 
				      int port);



extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;

extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;

extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;



extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
@@ -484,6 +497,7 @@ static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 
}



static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};

static const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {};

static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};



static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};

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