Commit 85474441 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Identify active requests 



To allow requests to forgo a common execution timeline, one question we
need to be able to answer is "is this request running?". To track
whether a request has started on HW, we can emit a breadcrumb at the
beginning of the request and check its timeline's HWSP to see if the
breadcrumb has advanced past the start of this request. (This is in
contrast to the global timeline where we need only ask if we are on the
global timeline and if the timeline has advanced past the end of the
previous request.)

There is still confusion from a preempted request, which has already
started but relinquished the HW to a high priority request. For the
common case, this discrepancy should be negligible. However, for
identification of hung requests, knowing which one was running at the
time of the hang will be much more important.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190129185452.20989-2-chris@chris-wilson.co.uk
parent 06039d98

drivers/gpu/drm/i915/i915_gem.c

+15 −0
Original line number Diff line number Diff line
@@ -2871,6 +2871,14 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, 
	return 0;

}



static bool match_ring(struct i915_request *rq)

{

	struct drm_i915_private *dev_priv = rq->i915;

	u32 ring = I915_READ(RING_START(rq->engine->mmio_base));



	return ring == i915_ggtt_offset(rq->ring->vma);

}



struct i915_request *

i915_gem_find_active_request(struct intel_engine_cs *engine)

{
@@ -2893,6 +2901,13 @@ i915_gem_find_active_request(struct intel_engine_cs *engine) 
		if (i915_request_completed(request))

			continue;



		if (!i915_request_started(request))

			break;



		/* More than one preemptible request may match! */

		if (!match_ring(request))

			break;



		active = request;

		break;

	}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+12 −0
Original line number Diff line number Diff line
@@ -1976,6 +1976,18 @@ static int eb_submit(struct i915_execbuffer *eb) 
			return err;

	}



	/*

	 * After we completed waiting for other engines (using HW semaphores)

	 * then we can signal that this request/batch is ready to run. This

	 * allows us to determine if the batch is still waiting on the GPU

	 * or actually running by checking the breadcrumb.

	 */

	if (eb->engine->emit_init_breadcrumb) {

		err = eb->engine->emit_init_breadcrumb(eb->request);

		if (err)

			return err;

	}



	err = eb->engine->emit_bb_start(eb->request,

					eb->batch->node.start +

					eb->batch_start_offset,

drivers/gpu/drm/i915/i915_request.c

+5 −5
Original line number Diff line number Diff line
@@ -333,7 +333,7 @@ void i915_request_retire_upto(struct i915_request *rq) 


static u32 timeline_get_seqno(struct i915_timeline *tl)

{

	return ++tl->seqno;

	return tl->seqno += 1 + tl->has_initial_breadcrumb;

}



static void move_to_timeline(struct i915_request *request,
@@ -382,7 +382,7 @@ void __i915_request_submit(struct i915_request *request) 
		intel_engine_enable_signaling(request, false);

	spin_unlock(&request->lock);



	engine->emit_breadcrumb(request,

	engine->emit_fini_breadcrumb(request,

				     request->ring->vaddr + request->postfix);



	/* Transfer from per-context onto the global per-engine timeline */
@@ -657,7 +657,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) 
	 * around inside i915_request_add() there is sufficient space at

	 * the beginning of the ring as well.

	 */

	rq->reserved_space = 2 * engine->emit_breadcrumb_dw * sizeof(u32);

	rq->reserved_space = 2 * engine->emit_fini_breadcrumb_dw * sizeof(u32);



	/*

	 * Record the position of the start of the request so that
@@ -908,7 +908,7 @@ void i915_request_add(struct i915_request *request) 
	 * GPU processing the request, we never over-estimate the

	 * position of the ring's HEAD.

	 */

	cs = intel_ring_begin(request, engine->emit_breadcrumb_dw);

	cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_dw);

	GEM_BUG_ON(IS_ERR(cs));

	request->postfix = intel_ring_offset(request, cs);

drivers/gpu/drm/i915/i915_request.h

+1 −0
Original line number Diff line number Diff line
@@ -344,6 +344,7 @@ static inline bool i915_request_started(const struct i915_request *rq) 
	if (i915_request_signaled(rq))

		return true;



	/* Remember: started but may have since been preempted! */

	return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);

}

drivers/gpu/drm/i915/i915_timeline.c

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ int i915_timeline_init(struct drm_i915_private *i915, 
	timeline->i915 = i915;

	timeline->name = name;

	timeline->pin_count = 0;

	timeline->has_initial_breadcrumb = !hwsp;



	timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;

	if (!hwsp) {

CRA Git | Maintained and supported by SUSTech CRA and CCSE