Commit 85119c16 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes 

Daniel writes:

" Nothing too major:
- A few fixes around the edid handling from Jani, also fixing a regression
  in 3.5 due to us using gmbus by default.
- Fixup hsw uncached pte flags.
- Fix suspend/resume crash when using hw contexts, from Ben.
- Try to tune gpu turbo a bit better, seems to help with some oddball
  power regressions."

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: use hsw rps tuning values everywhere on gen6+
  drm/i915: fall back to bit-banging if GMBUS fails in CRT EDID reads
  drm/i915: extract connector update from intel_ddc_get_modes() for reuse
  drm/i915: fix hsw uncached pte
  drm/i915/contexts: fix list corruption
  drm/i915: fix EDID memory leak in SDVO
parents e2be2cd8 1ee9ae32

drivers/char/agp/intel-agp.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
#define I830_PTE_SYSTEM_CACHED  0x00000006

/* GT PTE cache control fields */

#define GEN6_PTE_UNCACHED	0x00000002

#define HSW_PTE_UNCACHED	0x00000000

#define GEN6_PTE_LLC		0x00000004

#define GEN6_PTE_LLC_MLC	0x00000006

#define GEN6_PTE_GFDT		0x00000008

drivers/char/agp/intel-gtt.c

+69 −36
Original line number Diff line number Diff line
@@ -1156,6 +1156,30 @@ static bool gen6_check_flags(unsigned int flags) 
	return true;

}



static void haswell_write_entry(dma_addr_t addr, unsigned int entry,

				unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	} else { /* set 'normal'/'cached' to LLC by default */

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);

}



static void gen6_write_entry(dma_addr_t addr, unsigned int entry,

			     unsigned int flags)

{
@@ -1382,6 +1406,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { 
	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver haswell_gtt_driver = {

	.gen = 6,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = haswell_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver valleyview_gtt_driver = {

	.gen = 7,

	.setup = i9xx_setup,
@@ -1499,77 +1532,77 @@ static const struct intel_gtt_driver_description { 
	{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,

	    "ValleyView", &valleyview_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ 0, NULL, NULL }

};

drivers/gpu/drm/i915/i915_gem.c

+4 −4
Original line number Diff line number Diff line
@@ -2365,6 +2365,10 @@ int i915_gpu_idle(struct drm_device *dev) 


	/* Flush everything onto the inactive list. */

	for_each_ring(ring, dev_priv, i) {

		ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);

		if (ret)

			return ret;



		ret = i915_ring_idle(ring);

		if (ret)

			return ret;
@@ -2372,10 +2376,6 @@ int i915_gpu_idle(struct drm_device *dev) 
		/* Is the device fubar? */

		if (WARN_ON(!list_empty(&ring->gpu_write_list)))

			return -EBUSY;



		ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);

		if (ret)

			return ret;

	}



	return 0;

drivers/gpu/drm/i915/i915_gem_gtt.c

+4 −1
Original line number Diff line number Diff line
@@ -261,6 +261,9 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 
		pte_flags |= GEN6_PTE_CACHE_LLC;

		break;

	case I915_CACHE_NONE:

		if (IS_HASWELL(dev))

			pte_flags |= HSW_PTE_UNCACHED;

		else

			pte_flags |= GEN6_PTE_UNCACHED;

		break;

	default:

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ 


#define GEN6_PTE_VALID			(1 << 0)

#define GEN6_PTE_UNCACHED		(1 << 1)

#define HSW_PTE_UNCACHED		(0)

#define GEN6_PTE_CACHE_LLC		(2 << 1)

#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)

#define GEN6_PTE_CACHE_BITS		(3 << 1)

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