Commit 8510e726 authored Jan 07, 2014 by Laurent Pinchart Committed by Mike Turquette Feb 18, 2014

clk: shmobile: rcar-gen2: Fix qspi divisor



The qspi clock divisor is incorrectly set to twice the value it should
have, possibly because it has been computed based on PLL1 as the clock
parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal
frequencies, not the divisor values). Fix it.

Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

parent 995a9190

drivers/clk/shmobile/clk-rcar-gen2.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -215,7 +215,7 @@ rcar_gen2_cpg_register_clock(struct device_node np, struct rcar_gen2_cpg cpg,
		} else if (!strcmp(name, "qspi")) {
		parent_name = "pll1_div2";
		div = (cpg_mode & (BIT(3) \| BIT(2) \| BIT(1))) == BIT(2)
		? 16 : 20;
		? 8 : 10;
		} else if (!strcmp(name, "sdh")) {
		parent_name = "pll1_div2";
		table = cpg_sdh_div_table;

Admin message