Commit 84e7fc05 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: rename dccg to clk_mgr 



In preparation for adding the actual dccg block since the
current implementation of dccg is mor eof a clock manager
than a hw block

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 98e90a34

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -2071,7 +2071,7 @@ void dc_resource_state_construct( 
		const struct dc *dc,

		struct dc_state *dst_ctx)

{

	dst_ctx->dccg = dc->res_pool->dccg;

	dst_ctx->dccg = dc->res_pool->clk_mgr;

}



enum dc_status dc_validate_global_state(

drivers/gpu/drm/amd/display/dc/dce/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 


DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \

dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \

dce_dccg.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \

dce_clk_mgr.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \

dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o



AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))

drivers/gpu/drm/amd/display/dc/dce/dce_dccg.h→drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h

+29 −29
Original line number Diff line number Diff line
@@ -24,10 +24,10 @@ 
 */





#ifndef _DCE_DCCG_H_

#define _DCE_DCCG_H_

#ifndef _DCE_CLK_MGR_H_

#define _DCE_CLK_MGR_H_



#include "dccg.h"

#include "../inc/hw/clk_mgr.h"



#define MEMORY_TYPE_MULTIPLIER_CZ 4
@@ -55,15 +55,15 @@ 
	type DENTIST_DISPCLK_WDIVIDER; \

	type DENTIST_DISPCLK_CHG_DONE;



struct dccg_shift {

struct clk_mgr_shift {

	CLK_REG_FIELD_LIST(uint8_t)

};



struct dccg_mask {

struct clk_mgr_mask {

	CLK_REG_FIELD_LIST(uint32_t)

};



struct dccg_registers {

struct clk_mgr_registers {

	uint32_t DPREFCLK_CNTL;

	uint32_t DENTIST_DISPCLK_CNTL;

};
@@ -73,11 +73,11 @@ struct state_dependent_clocks { 
	int pixel_clk_khz;

};



struct dce_dccg {

	struct dccg base;

	const struct dccg_registers *regs;

	const struct dccg_shift *dccg_shift;

	const struct dccg_mask *dccg_mask;

struct dce_clk_mgr {

	struct clk_mgr base;

	const struct clk_mgr_registers *regs;

	const struct clk_mgr_shift *clk_mgr_shift;

	const struct clk_mgr_mask *clk_mgr_mask;



	struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
@@ -130,36 +130,36 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl 
	return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);

}



void dce_clock_read_ss_info(struct dce_dccg *dccg_dce);

void dce_clock_read_ss_info(struct dce_clk_mgr *dccg_dce);



int dce12_get_dp_ref_freq_khz(struct dccg *dccg);

int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);



void dce110_fill_display_configs(

	const struct dc_state *context,

	struct dm_pp_display_configuration *pp_display_cfg);



int dce112_set_clock(struct dccg *dccg, int requested_clk_khz);

int dce112_set_clock(struct clk_mgr *dccg, int requested_clk_khz);



struct dccg *dce_dccg_create(

struct clk_mgr *dce_clk_mgr_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);

	const struct clk_mgr_registers *regs,

	const struct clk_mgr_shift *clk_shift,

	const struct clk_mgr_mask *clk_mask);



struct dccg *dce110_dccg_create(

struct clk_mgr *dce110_clk_mgr_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);

	const struct clk_mgr_registers *regs,

	const struct clk_mgr_shift *clk_shift,

	const struct clk_mgr_mask *clk_mask);



struct dccg *dce112_dccg_create(

struct clk_mgr *dce112_clk_mgr_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *clk_shift,

	const struct dccg_mask *clk_mask);

	const struct clk_mgr_registers *regs,

	const struct clk_mgr_shift *clk_shift,

	const struct clk_mgr_mask *clk_mask);



struct dccg *dce120_dccg_create(struct dc_context *ctx);

struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx);



void dce_dccg_destroy(struct dccg **dccg);

void dce_clk_mgr_destroy(struct clk_mgr **dccg);



#endif /* _DCE_DCCG_H_ */
 
#endif /* _DCE_CLK_MGR_H_ */

drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

+2 −2
Original line number Diff line number Diff line
@@ -111,8 +111,8 @@ void dce100_prepare_bandwidth( 
{

	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);



	dc->res_pool->dccg->funcs->update_clocks(

			dc->res_pool->dccg,

	dc->res_pool->clk_mgr->funcs->update_clocks(

			dc->res_pool->clk_mgr,

			context,

			false);

}

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