Commit 84cc8a71 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin into next/dt 

Merge "ARM: berlin: DT changes for v3.16" from Sebastian Hesselbart:

Quite a lot changes but it looks like DT approach is really paying off.
BG2Q joins Berlin SoC family with corresponding development board, DW
gpio nodes for all SoCs. Most notably, we have settled clock bindings
to allow us to continue on drivers requiring clocks and pinctrl bindings.
Last but not least, BG2Q gained SDHCI support and is able to properly
boot into userspace.

* tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin

:
  ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP
  ARM: dts: berlin: add the SDHCI nodes for the BG2Q
  ARM: dts: berlin: add the pinctrl node and muxing setup for uarts
  dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
  ARM: dts: berlin: convert BG2Q to DT clock nodes
  ARM: dts: berlin: convert BG2 to DT clock nodes
  ARM: dts: berlin: convert BG2CD to DT clock nodes
  clk: berlin: add binding include for Berlin SoC clock ids
  dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs
  ARM: dts: berlin: add the BG2CD GPIO nodes
  ARM: dts: berlin: add the BG2 GPIO nodes
  ARM: dts: berlin: add the BG2Q GPIO nodes
  ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q
  ARM: dts: berlin: add the Marvell BG2-Q DMP device tree
  ARM: dts: berlin: add the Marvell Armada 1500 pro

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f5196776 3047086d

Documentation/devicetree/bindings/arm/marvell,berlin.txt

+102 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are: 
    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),

    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)

    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)

    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)

    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)



* Example:
@@ -22,3 +23,104 @@ SoC and board used. Currently known SoC compatibles are: 


	...

}



* Marvell Berlin2 chip control binding



Marvell Berlin SoCs have a chip control register set providing several

individual registers dealing with pinmux, padmux, clock, reset, and secondary

CPU boot address. Unfortunately, the individual registers are spread among the

chip control registers, so there should be a single DT node only providing the

different functions which are described below.



Required properties:

- compatible: shall be one of

	"marvell,berlin2-chip-ctrl" for BG2

	"marvell,berlin2cd-chip-ctrl" for BG2CD

	"marvell,berlin2q-chip-ctrl" for BG2Q

- reg: address and length of following register sets for

  BG2/BG2CD: chip control register set

  BG2Q: chip control register set and cpu pll registers



* Marvell Berlin2 system control binding



Marvell Berlin SoCs have a system control register set providing several

individual registers dealing with pinmux, padmux, and reset.



Required properties:

- compatible: should be one of

	"marvell,berlin2-system-ctrl" for BG2

	"marvell,berlin2cd-system-ctrl" for BG2CD

	"marvell,berlin2q-system-ctrl" for BG2Q

- reg: address and length of the system control register set



* Clock provider binding



As clock related registers are spread among the chip control registers, the

chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)

SoCs share the same IP for PLLs and clocks, with some minor differences in

features and register layout.



Required properties:

- #clock-cells: shall be set to 1

- clocks: clock specifiers referencing the core clock input clocks

- clock-names: array of strings describing the input clock specifiers above.

    Allowed clock-names for the reference clocks are

      "refclk" for the SoCs osciallator input on all SoCs,

    and SoC-specific input clocks for

      BG2/BG2CD: "video_ext0" for the external video clock input



Clocks provided by core clocks shall be referenced by a clock specifier

indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h

for the corresponding index mapping.



* Pin controller binding



Pin control registers are part of both register sets, chip control and system

control. The pins controlled are organized in groups, so no actual pin

information is needed.



A pin-controller node should contain subnodes representing the pin group

configurations, one per function. Each subnode has the group name and the muxing

function used.



Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called

a 'function' in the pin-controller subsystem.



Required subnode-properties:

- groups: a list of strings describing the group names.

- function: a string describing the function used to mux the groups.



Example:



chip: chip-control@ea0000 {

	compatible = "marvell,berlin2-chip-ctrl";

	#clock-cells = <1>;

	reg = <0xea0000 0x400>;

	clocks = <&refclk>, <&externaldev 0>;

	clock-names = "refclk", "video_ext0";



	spi1_pmux: spi1-pmux {

		groups = "G0";

		function = "spi1";

	};

};



sysctrl: system-controller@d000 {

	compatible = "marvell,berlin2-system-ctrl";

	reg = <0xd000 0x100>;



	uart0_pmux: uart0-pmux {

		groups = "GSM4";

		function = "uart0";

	};



	uart1_pmux: uart1-pmux {

		groups = "GSM5";

		function = "uart1";

	};



	uart2_pmux: uart2-pmux {

		groups = "GSM3";

		function = "uart2";

	};

};

arch/arm/boot/dts/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 
	bcm21664-garnet.dtb

dtb-$(CONFIG_ARCH_BERLIN) += \

	berlin2-sony-nsz-gs7.dtb	\

	berlin2cd-google-chromecast.dtb

	berlin2cd-google-chromecast.dtb	\

	berlin2q-marvell-dmp.dtb

dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \

	da850-evm.dtb

dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb

arch/arm/boot/dts/berlin2.dtsi

+161 −30
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
 */



#include "skeleton.dtsi"

#include <dt-bindings/clock/berlin2.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {
@@ -37,26 +38,12 @@ 
		};

	};



	clocks {

		smclk: sysmgr-clock {

	refclk: oscillator {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <25000000>;

	};



		cfgclk: cfg-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <100000000>;

		};



		sysclk: system-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <400000000>;

		};

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -72,6 +59,11 @@ 
			cache-level = <2>;

		};



		scu: snoop-control-unit@ad0000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0xad0000 0x58>;

		};



		gic: interrupt-controller@ad1000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@@ -83,7 +75,7 @@ 
			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xad0600 0x20>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sysclk>;

			clocks = <&chip CLKID_TWD>;

		};



		apb@e80000 {
@@ -94,11 +86,83 @@ 
			ranges = <0 0xe80000 0x10000>;

			interrupt-parent = <&aic>;



			gpio0: gpio@0400 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0400 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porta: gpio-port@0 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <0>;

				};

			};



			gpio1: gpio@0800 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0800 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portb: gpio-port@1 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <1>;

				};

			};



			gpio2: gpio@0c00 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0c00 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portc: gpio-port@2 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <2>;

				};

			};



			gpio3: gpio@1000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x1000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portd: gpio-port@3 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <3>;

				};

			};



			timer0: timer@2c00 {

				compatible = "snps,dw-apb-timer";

				reg = <0x2c00 0x14>;

				interrupts = <8>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "okay";

			};
@@ -107,7 +171,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c14 0x14>;

				interrupts = <9>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "okay";

			};
@@ -116,7 +180,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c28 0x14>;

				interrupts = <10>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -125,7 +189,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c3c 0x14>;

				interrupts = <11>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -134,7 +198,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c50 0x14>;

				interrupts = <12>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -143,7 +207,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c64 0x14>;

				interrupts = <13>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -152,7 +216,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c78 0x14>;

				interrupts = <14>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -161,7 +225,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c8c 0x14>;

				interrupts = <15>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -176,6 +240,14 @@ 
			};

		};



		chip: chip-control@ea0000 {

			compatible = "marvell,berlin2-chip-ctrl";

			#clock-cells = <1>;

			reg = <0xea0000 0x400>;

			clocks = <&refclk>;

			clock-names = "refclk";

		};



		apb@fc0000 {

			compatible = "simple-bus";

			#address-cells = <1>;
@@ -184,13 +256,48 @@ 
			ranges = <0 0xfc0000 0x10000>;

			interrupt-parent = <&sic>;



			sm_gpio1: gpio@5000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x5000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

				};

			};



			sm_gpio0: gpio@c000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0xc000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <11>;

				};

			};



			uart0: serial@9000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x9000 0x100>;

				reg-shift = <2>;

				reg-io-width = <1>;

				interrupts = <8>;

				clocks = <&smclk>;

				clocks = <&refclk>;

				pinctrl-0 = <&uart0_pmux>;

				pinctrl-names = "default";

				status = "disabled";

			};
@@ -200,7 +307,9 @@ 
				reg-shift = <2>;

				reg-io-width = <1>;

				interrupts = <9>;

				clocks = <&smclk>;

				clocks = <&refclk>;

				pinctrl-0 = <&uart1_pmux>;

				pinctrl-names = "default";

				status = "disabled";

			};
@@ -210,10 +319,32 @@ 
				reg-shift = <2>;

				reg-io-width = <1>;

				interrupts = <10>;

				clocks = <&smclk>;

				clocks = <&refclk>;

				pinctrl-0 = <&uart2_pmux>;

				pinctrl-names = "default";

				status = "disabled";

			};



			sysctrl: system-controller@d000 {

				compatible = "marvell,berlin2-system-ctrl";

				reg = <0xd000 0x100>;



				uart0_pmux: uart0-pmux {

					groups = "GSM4";

					function = "uart0";

				};



				uart1_pmux: uart1-pmux {

					groups = "GSM5";

					function = "uart1";

				};



				uart2_pmux: uart2-pmux {

					groups = "GSM3";

					function = "uart2";

				};

			};



			sic: interrupt-controller@e000 {

				compatible = "snps,dw-apb-ictl";

				reg = <0xe000 0x400>;

arch/arm/boot/dts/berlin2cd.dtsi

+138 −29
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
 */



#include "skeleton.dtsi"

#include <dt-bindings/clock/berlin2.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {
@@ -30,26 +31,12 @@ 
		};

	};



	clocks {

		smclk: sysmgr-clock {

	refclk: oscillator {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <25000000>;

	};



		cfgclk: cfg-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <75000000>;

		};



		sysclk: system-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <300000000>;

		};

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -76,7 +63,7 @@ 
			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xad0600 0x20>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sysclk>;

			clocks = <&chip CLKID_TWD>;

		};



		apb@e80000 {
@@ -87,11 +74,83 @@ 
			ranges = <0 0xe80000 0x10000>;

			interrupt-parent = <&aic>;



			gpio0: gpio@0400 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0400 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porta: gpio-port@0 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <0>;

				};

			};



			gpio1: gpio@0800 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0800 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portb: gpio-port@1 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <1>;

				};

			};



			gpio2: gpio@0c00 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0c00 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portc: gpio-port@2 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <2>;

				};

			};



			gpio3: gpio@1000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x1000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portd: gpio-port@3 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <3>;

				};

			};



			timer0: timer@2c00 {

				compatible = "snps,dw-apb-timer";

				reg = <0x2c00 0x14>;

				interrupts = <8>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "okay";

			};
@@ -100,7 +159,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c14 0x14>;

				interrupts = <9>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "okay";

			};
@@ -109,7 +168,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c28 0x14>;

				interrupts = <10>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -118,7 +177,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c3c 0x14>;

				interrupts = <11>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -127,7 +186,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c50 0x14>;

				interrupts = <12>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -136,7 +195,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c64 0x14>;

				interrupts = <13>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -145,7 +204,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c78 0x14>;

				interrupts = <14>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -154,7 +213,7 @@ 
				compatible = "snps,dw-apb-timer";

				reg = <0x2c8c 0x14>;

				interrupts = <15>;

				clocks = <&cfgclk>;

				clocks = <&chip CLKID_CFG>;

				clock-names = "timer";

				status = "disabled";

			};
@@ -169,6 +228,19 @@ 
			};

		};



		chip: chip-control@ea0000 {

			compatible = "marvell,berlin2cd-chip-ctrl";

			#clock-cells = <1>;

			reg = <0xea0000 0x400>;

			clocks = <&refclk>;

			clock-names = "refclk";



			uart0_pmux: uart0-pmux {

				groups = "G6";

				function = "uart0";

			};

		};



		apb@fc0000 {

			compatible = "simple-bus";

			#address-cells = <1>;
@@ -177,13 +249,45 @@ 
			ranges = <0 0xfc0000 0x10000>;

			interrupt-parent = <&sic>;



			sm_gpio1: gpio@5000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x5000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

				};

			};



			sm_gpio0: gpio@c000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0xc000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

				};

			};



			uart0: serial@9000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x9000 0x100>;

				reg-shift = <2>;

				reg-io-width = <1>;

				interrupts = <8>;

				clocks = <&smclk>;

				clocks = <&refclk>;

				pinctrl-0 = <&uart0_pmux>;

				pinctrl-names = "default";

				status = "disabled";

			};
@@ -193,10 +297,15 @@ 
				reg-shift = <2>;

				reg-io-width = <1>;

				interrupts = <9>;

				clocks = <&smclk>;

				clocks = <&refclk>;

				status = "disabled";

			};



			sysctrl: system-controller@d000 {

				compatible = "marvell,berlin2cd-system-ctrl";

				reg = <0xd000 0x100>;

			};



			sic: interrupt-controller@e000 {

				compatible = "snps,dw-apb-ictl";

				reg = <0xe000 0x400>;

arch/arm/boot/dts/berlin2q-marvell-dmp.dts

0 → 100644
+39 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



/dts-v1/;

#include "berlin2q.dtsi"



/ {

	model = "Marvell BG2-Q DMP";

	compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";



	memory {

		device_type = "memory";

		reg = <0x00000000 0x80000000>;

	};



	choosen {

		bootargs = "console=ttyS0,115200 earlyprintk";

	};

};



&sdhci1 {

	broken-cd;

	sdhci,wp-inverted;

	status = "okay";

};



&sdhci2 {

	non-removable;

	status = "okay";

};



&uart0 {

	status = "okay";

};

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