drm/msm/a6xx: Add support for per-instance pagetables (84c31ee1) · Commits · 戴 / test

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+62 −0

Original line number	Diff line number	Diff line
		@@ -81,6 +81,49 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
		OUT_RING(ring, upper_32_bits(iova));
		}

		static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
		struct msm_ringbuffer ring, struct msm_file_private ctx)
		{
		phys_addr_t ttbr;
		u32 asid;
		u64 memptr = rbmemptr(ring, ttbr0);

		if (ctx == a6xx_gpu->cur_ctx)
		return;

		if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
		return;

		/* Execute the table update */
		OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));

		OUT_RING(ring,
		CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) \|
		CP_SMMU_TABLE_UPDATE_1_ASID(asid));
		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));

		/*
		* Write the new TTBR0 to the memstore. This is good for debugging.
		*/
		OUT_PKT7(ring, CP_MEM_WRITE, 4);
		OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
		OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
		OUT_RING(ring, lower_32_bits(ttbr));
		OUT_RING(ring, (asid << 16) \| upper_32_bits(ttbr));

		/*
		* And finally, trigger a uche flush to be sure there isn't anything
		* lingering in that part of the GPU
		*/

		OUT_PKT7(ring, CP_EVENT_WRITE, 1);
		OUT_RING(ring, 0x31);

		a6xx_gpu->cur_ctx = ctx;
		}

		static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit)
		{
		unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
		@@ -90,6 +133,8 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit)
		struct msm_ringbuffer *ring = submit->ring;
		unsigned int i;

		a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);

		get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
		rbmemptr_stats(ring, index, cpcycles_start));

		@@ -704,6 +749,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		/* Always come up on rb 0 */
		a6xx_gpu->cur_ring = gpu->rb[0];

		a6xx_gpu->cur_ctx = NULL;

		/* Enable the SQE_to start the CP engine */
		gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);

		@@ -1020,6 +1067,20 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
		return (unsigned long)busy_time;
		}

		static struct msm_gem_address_space *
		a6xx_create_private_address_space(struct msm_gpu *gpu)
		{
		struct msm_mmu *mmu;

		mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);

		if (IS_ERR(mmu))
		return ERR_CAST(mmu);

		return msm_gem_address_space_create(mmu,
		"gpu", 0x100000000ULL, 0x1ffffffffULL);
		}

		static const struct adreno_gpu_funcs funcs = {
		.base = {
		.get_param = adreno_get_param,
		@@ -1043,6 +1104,7 @@ static const struct adreno_gpu_funcs funcs = {
		.gpu_state_put = a6xx_gpu_state_put,
		#endif
		.create_address_space = adreno_iommu_create_address_space,
		.create_private_address_space = a6xx_create_private_address_space,
		},
		.get_timestamp = a6xx_get_timestamp,
		};

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@ struct a6xx_gpu {
		uint64_t sqe_iova;

		struct msm_ringbuffer *cur_ring;
		struct msm_file_private *cur_ctx;

		struct a6xx_gmu gmu;
		};

drivers/gpu/drm/msm/msm_ringbuffer.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -31,6 +31,7 @@ struct msm_rbmemptrs {
		volatile uint32_t fence;

		volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];
		volatile u64 ttbr0;
		};

		struct msm_ringbuffer {

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