Commit 8471a202 authored by Ludovic Barre's avatar Ludovic Barre Committed by Alexandre Torgue
Browse files

ARM: dts: stm32: add stm32mp157c initial support 



Add stm32mp157c initial support with:
-Dual Cortex-A7
-Arm psci, timer, gic
-Pinctrl
-Uart

Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
parent a4501195

arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

0 → 100644
+172 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved

 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.

 */

#include <dt-bindings/pinctrl/stm32-pinfunc.h>



/ {

	soc {

		pinctrl: pin-controller {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "st,stm32mp157-pinctrl";

			ranges = <0 0x50002000 0xa400>;

			pins-are-numbered;



			gpioa: gpio@50002000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x0 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOA";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 0 16>;

			};



			gpiob: gpio@50003000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x1000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOB";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 16 16>;

			};



			gpioc: gpio@50004000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x2000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOC";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 32 16>;

			};



			gpiod: gpio@50005000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x3000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOD";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 48 16>;

			};



			gpioe: gpio@50006000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x4000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOE";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 64 16>;

			};



			gpiof: gpio@50007000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x5000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOF";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 80 16>;

			};



			gpiog: gpio@50008000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x6000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOG";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 96 16>;

			};



			gpioh: gpio@50009000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x7000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOH";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 112 16>;

			};



			gpioi: gpio@5000a000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x8000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOI";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 128 16>;

			};



			gpioj: gpio@5000b000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0x9000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOJ";

				ngpios = <16>;

				gpio-ranges = <&pinctrl 0 144 16>;

			};



			gpiok: gpio@5000c000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0xa000 0x400>;

				clocks = <&clk_pll3_p>;

				st,bank-name = "GPIOK";

				ngpios = <8>;

				gpio-ranges = <&pinctrl 0 160 8>;

			};

		};



		pinctrl_z: pin-controller-z {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "st,stm32mp157-z-pinctrl";

			ranges = <0 0x54004000 0x400>;

			pins-are-numbered;

			status = "disabled";



			gpioz: gpio@54004000 {

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg = <0 0x400>;

				clocks = <&clk_pll2_p>;

				st,bank-name = "GPIOZ";

				st,bank-ioport = <11>;

				ngpios = <8>;

				gpio-ranges = <&pinctrl_z 0 400 8>;

			};

		};

	};

};

arch/arm/boot/dts/stm32mp157c.dtsi

0 → 100644
+194 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved

 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

		};



		cpu1: cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};

	};



	psci {

		compatible = "arm,psci";

		method = "smc";

		cpu_off = <0x84000002>;

		cpu_on = <0x84000003>;

	};



	aliases {

		gpio0 = &gpioa;

		gpio1 = &gpiob;

		gpio2 = &gpioc;

		gpio3 = &gpiod;

		gpio4 = &gpioe;

		gpio5 = &gpiof;

		gpio6 = &gpiog;

		gpio7 = &gpioh;

		gpio8 = &gpioi;

		gpio9 = &gpioj;

		gpio10 = &gpiok;

	};



	intc: interrupt-controller@a0021000 {

		compatible = "arm,cortex-a7-gic";

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0xa0021000 0x1000>,

		      <0xa0022000 0x2000>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&intc>;

	};



	clocks {

		clk_hse: clk-hse {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};



		clk_pll_per: clk-pll-per {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <64000000>;

		};



		clk_hsi: clk-hsi {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <64000000>;

		};



		clk_lse: clk-lse {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

		};



		clk_lsi: clk-lsi {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32000>;

		};



		clk_csi: clk-csi {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <4000000>;

		};



		clk_pclk1: clk-pclk1 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <86000000>;

		};



		clk_pll3_p: clk-pll3_p {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <172000000>;

		};



		clk_pll2_p: clk-pll2_p {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <264000000>;

		};

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&intc>;

		ranges;



		usart2: serial@4000e000 {

			compatible = "st,stm32h7-uart";

			reg = <0x4000e000 0x400>;

			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		usart3: serial@4000f000 {

			compatible = "st,stm32h7-uart";

			reg = <0x4000f000 0x400>;

			interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		uart4: serial@40010000 {

			compatible = "st,stm32h7-uart";

			reg = <0x40010000 0x400>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		uart5: serial@40011000 {

			compatible = "st,stm32h7-uart";

			reg = <0x40011000 0x400>;

			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		uart7: serial@40018000 {

			compatible = "st,stm32h7-uart";

			reg = <0x40018000 0x400>;

			interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		uart8: serial@40019000 {

			compatible = "st,stm32h7-uart";

			reg = <0x40019000 0x400>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		usart6: serial@44003000 {

			compatible = "st,stm32h7-uart";

			reg = <0x44003000 0x400>;

			interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};



		usart1: serial@5c000000 {

			compatible = "st,stm32h7-uart";

			reg = <0x5c000000 0x400>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;

			clocks = <&clk_pclk1>;

			status = "disabled";

		};

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE