Commit 840c90fc authored by Thomas Anderson's avatar Thomas Anderson Committed by Alex Deucher
Browse files

drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded 



For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
"interesting" modes would be disabled, leaving only low-res or low
framerate modes.

This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
clock is exceeded. Verified that 8K30 and 4K120 are now available and
working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarThomas Anderson <thomasanderson@google.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7aec9ec1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+23 −22
Original line number Diff line number Diff line
@@ -3356,27 +3356,21 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 
	return color_space;

}



static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)

{

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;



	timing_out->display_color_depth--;

}



static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,

static bool adjust_colour_depth_from_display_info(

	struct dc_crtc_timing *timing_out,

	const struct drm_display_info *info)

{

	enum dc_color_depth depth = timing_out->display_color_depth;

	int normalized_clk;

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;

	do {

		normalized_clk = timing_out->pix_clk_100hz / 10;

		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */

		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)

			normalized_clk /= 2;

		/* Adjusting pix clock following on HDMI spec based on colour depth */

		switch (timing_out->display_color_depth) {

		switch (depth) {

		case COLOR_DEPTH_888:

			break;

		case COLOR_DEPTH_101010:

			normalized_clk = (normalized_clk * 30) / 24;

			break;
@@ -3387,14 +3381,15 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_ 
			normalized_clk = (normalized_clk * 48) / 24;

			break;

		default:

			return;

			/* The above depths are the only ones valid for HDMI. */

			return false;

		}

		if (normalized_clk <= info->max_tmds_clock)

			return;

		reduce_mode_colour_depth(timing_out);



	} while (timing_out->display_color_depth > COLOR_DEPTH_888);



		if (normalized_clk <= info->max_tmds_clock) {

			timing_out->display_color_depth = depth;

			return true;

		}

	} while (--depth > COLOR_DEPTH_666);

	return false;

}



static void fill_stream_properties_from_drm_display_mode(
@@ -3474,9 +3469,15 @@ static void fill_stream_properties_from_drm_display_mode( 


	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {

		if (!adjust_colour_depth_from_display_info(timing_out, info) &&

		    drm_mode_is_420_also(info, mode_in) &&

		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {

			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;

			adjust_colour_depth_from_display_info(timing_out, info);

		}

	}

}



static void fill_audio_info(struct audio_info *audio_info,

			    const struct drm_connector *drm_connector,

CRA Git | Maintained and supported by SUSTech CRA and CCSE