Commit 83e7d2ec authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions 



Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 48e1f50b

arch/arm64/boot/dts/renesas/r8a77990.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
 * Copyright (C) 2018 Renesas Electronics Corp.

 */



#include <dt-bindings/clock/renesas-cpg-mssr.h>

#include <dt-bindings/clock/r8a77990-cpg-mssr.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/r8a77990-sysc.h>
@@ -22,7 +22,7 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0>;

			device_type = "cpu";

			power-domains = <&sysc 5>;

			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};
@@ -31,14 +31,14 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <1>;

			device_type = "cpu";

			power-domains = <&sysc 6>;

			power-domains = <&sysc R8A77990_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		L2_CA53: cache-controller-0 {

			compatible = "cache";

			power-domains = <&sysc 21>;

			power-domains = <&sysc R8A77990_PD_CA53_SCU>;

			cache-unified;

			cache-level = <2>;

		};
@@ -75,7 +75,7 @@ 
				     "renesas,rcar-gen3-wdt";

			reg = <0 0xe6020000 0 0x0c>;

			clocks = <&cpg CPG_MOD 402>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 402>;

			status = "disabled";

		};
@@ -91,7 +91,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 912>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 912>;

		};
@@ -106,7 +106,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 911>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 911>;

		};
@@ -121,7 +121,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 910>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 910>;

		};
@@ -136,7 +136,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 909>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 909>;

		};
@@ -151,7 +151,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 908>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 908>;

		};
@@ -166,7 +166,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 907>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 907>;

		};
@@ -181,7 +181,7 @@ 
			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 906>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 906>;

		};
@@ -329,7 +329,7 @@ 
					  "ch20", "ch21", "ch22", "ch23",

					  "ch24";

			clocks = <&cpg CPG_MOD 812>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			phy-mode = "rgmii";

			#address-cells = <1>;
@@ -414,7 +414,7 @@ 
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 310>;

			clock-names = "fck";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 310>;

			status = "disabled";

		};
@@ -437,7 +437,7 @@ 
			clocks = <&cpg CPG_MOD 703>;

			phys = <&usb2_phy0>;

			phy-names = "usb";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";

		};
@@ -450,7 +450,7 @@ 
			phys = <&usb2_phy0>;

			phy-names = "usb";

			companion = <&ohci0>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";

		};
@@ -461,7 +461,7 @@ 
			reg = <0 0xee080200 0 0x700>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			#phy-cells = <0>;

			status = "disabled";
@@ -480,7 +480,7 @@ 
					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 408>;

		};

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