Commit 83d7af64 authored by Giuseppe CAVALLARO's avatar Giuseppe CAVALLARO Committed by David S. Miller
Browse files

stmmac: dity-up and rework the driver debug levels 



Prior this patch, the internal debugging was based on ifdef
and also some printk were useless because many info are exposed
via ethtool.
This patch remove all the ifdef defines and now we only use
netif_msg_XXX levels.

Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 06a23fe3

drivers/net/ethernet/stmicro/stmmac/common.h

+0 −10
Original line number Diff line number Diff line
@@ -38,16 +38,6 @@ 
#include "descs.h"

#include "mmc.h"



#undef CHIP_DEBUG_PRINT

/* Turn-on extra printk debug for MAC core, dma and descriptors */

/* #define CHIP_DEBUG_PRINT */



#ifdef CHIP_DEBUG_PRINT

#define CHIP_DBG(fmt, args...)  printk(fmt, ## args)

#else

#define CHIP_DBG(fmt, args...)  do { } while (0)

#endif



/* Synopsys Core versions */

#define	DWMAC_CORE_3_40	0x34

#define	DWMAC_CORE_3_50	0x35

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+19 −38
Original line number Diff line number Diff line
@@ -91,8 +91,8 @@ static void dwmac1000_set_filter(struct net_device *dev, int id) 
	unsigned int value = 0;

	unsigned int perfect_addr_number;



	CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",

		 __func__, netdev_mc_count(dev), netdev_uc_count(dev));

	pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,

		 netdev_mc_count(dev), netdev_uc_count(dev));



	if (dev->flags & IFF_PROMISC)

		value = GMAC_FRAME_FILTER_PR;
@@ -152,7 +152,7 @@ static void dwmac1000_set_filter(struct net_device *dev, int id) 
#endif

	writel(value, ioaddr + GMAC_FRAME_FILTER);



	CHIP_DBG(KERN_INFO "\tFilter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",

	pr_debug("\tFilter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",

		 readl(ioaddr + GMAC_FRAME_FILTER),

		 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));

}
@@ -162,18 +162,18 @@ static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex, 
{

	unsigned int flow = 0;



	CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");

	pr_debug("GMAC Flow-Control:\n");

	if (fc & FLOW_RX) {

		CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");

		pr_debug("\tReceive Flow-Control ON\n");

		flow |= GMAC_FLOW_CTRL_RFE;

	}

	if (fc & FLOW_TX) {

		CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");

		pr_debug("\tTransmit Flow-Control ON\n");

		flow |= GMAC_FLOW_CTRL_TFE;

	}



	if (duplex) {

		CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);

		pr_debug("\tduplex mode: PAUSE %d\n", pause_time);

		flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);

	}
@@ -185,11 +185,11 @@ static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode) 
	unsigned int pmt = 0;



	if (mode & WAKE_MAGIC) {

		CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");

		pr_debug("GMAC: WOL Magic frame\n");

		pmt |= power_down | magic_pkt_en;

	}

	if (mode & WAKE_UCAST) {

		CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");

		pr_debug("GMAC: WOL on global unicast\n");

		pmt |= global_unicast;

	}
@@ -203,23 +203,13 @@ static int dwmac1000_irq_status(void __iomem *ioaddr, 
	int ret = 0;



	/* Not used events (e.g. MMC interrupts) are not handled. */

	if ((intr_status & mmc_tx_irq)) {

		CHIP_DBG(KERN_INFO "GMAC: MMC tx interrupt: 0x%08x\n",

			 readl(ioaddr + GMAC_MMC_TX_INTR));

	if ((intr_status & mmc_tx_irq))

		x->mmc_tx_irq_n++;

	}

	if (unlikely(intr_status & mmc_rx_irq)) {

		CHIP_DBG(KERN_INFO "GMAC: MMC rx interrupt: 0x%08x\n",

			 readl(ioaddr + GMAC_MMC_RX_INTR));

	if (unlikely(intr_status & mmc_rx_irq))

		x->mmc_rx_irq_n++;

	}

	if (unlikely(intr_status & mmc_rx_csum_offload_irq)) {

		CHIP_DBG(KERN_INFO "GMAC: MMC rx csum offload: 0x%08x\n",

			 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));

	if (unlikely(intr_status & mmc_rx_csum_offload_irq))

		x->mmc_rx_csum_offload_irq_n++;

	}

	if (unlikely(intr_status & pmt_irq)) {

		CHIP_DBG(KERN_INFO "GMAC: received Magic frame\n");

		/* clear the PMT bits 5 and 6 by reading the PMT status reg */

		readl(ioaddr + GMAC_PMT);

		x->irq_receive_pmt_irq_n++;
@@ -229,32 +219,22 @@ static int dwmac1000_irq_status(void __iomem *ioaddr, 
		/* Clean LPI interrupt by reading the Reg 12 */

		ret = readl(ioaddr + LPI_CTRL_STATUS);



		if (ret & LPI_CTRL_STATUS_TLPIEN) {

			CHIP_DBG(KERN_INFO "GMAC TX entered in LPI\n");

		if (ret & LPI_CTRL_STATUS_TLPIEN)

			x->irq_tx_path_in_lpi_mode_n++;

		}

		if (ret & LPI_CTRL_STATUS_TLPIEX) {

			CHIP_DBG(KERN_INFO "GMAC TX exit from LPI\n");

		if (ret & LPI_CTRL_STATUS_TLPIEX)

			x->irq_tx_path_exit_lpi_mode_n++;

		}

		if (ret & LPI_CTRL_STATUS_RLPIEN) {

			CHIP_DBG(KERN_INFO "GMAC RX entered in LPI\n");

		if (ret & LPI_CTRL_STATUS_RLPIEN)

			x->irq_rx_path_in_lpi_mode_n++;

		}

		if (ret & LPI_CTRL_STATUS_RLPIEX) {

			CHIP_DBG(KERN_INFO "GMAC RX exit from LPI\n");

		if (ret & LPI_CTRL_STATUS_RLPIEX)

			x->irq_rx_path_exit_lpi_mode_n++;

	}

	}



	if ((intr_status & pcs_ane_irq) || (intr_status & pcs_link_irq)) {

		CHIP_DBG(KERN_INFO "GMAC PCS ANE IRQ\n");

		readl(ioaddr + GMAC_AN_STATUS);

		x->irq_pcs_ane_n++;

	}

	if (intr_status & rgmii_irq) {

		u32 status = readl(ioaddr + GMAC_S_R_GMII);

		CHIP_DBG(KERN_INFO "GMAC RGMII/SGMII interrupt\n");

		x->irq_rgmii_n++;



		/* Save and dump the link status. */
@@ -271,11 +251,12 @@ static int dwmac1000_irq_status(void __iomem *ioaddr, 
				x->pcs_speed = SPEED_10;



			x->pcs_link = 1;

			pr_debug("Link is Up - %d/%s\n", (int)x->pcs_speed,

			pr_debug("%s: Link is Up - %d/%s\n", __func__,

				 (int)x->pcs_speed,

				 x->pcs_duplex ? "Full" : "Half");

		} else {

			x->pcs_link = 0;

			pr_debug("Link is Down\n");

			pr_debug("%s: Link is Down\n", __func__);

		}

	}

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+4 −6
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, 
	u32 csr6 = readl(ioaddr + DMA_CONTROL);



	if (txmode == SF_DMA_MODE) {

		CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");

		pr_debug("GMAC: enable TX store and forward mode\n");

		/* Transmit COE type 2 cannot be done in cut-through mode. */

		csr6 |= DMA_CONTROL_TSF;

		/* Operating on second frame increase the performance
@@ -124,8 +124,7 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, 
		 */

		csr6 |= DMA_CONTROL_OSF;

	} else {

		CHIP_DBG(KERN_DEBUG "GMAC: disabling TX SF (threshold %d)\n",

			 txmode);

		pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);

		csr6 &= ~DMA_CONTROL_TSF;

		csr6 &= DMA_CONTROL_TC_TX_MASK;

		/* Set the transmit threshold */
@@ -142,11 +141,10 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, 
	}



	if (rxmode == SF_DMA_MODE) {

		CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");

		pr_debug("GMAC: enable RX store and forward mode\n");

		csr6 |= DMA_CONTROL_RSF;

	} else {

		CHIP_DBG(KERN_DEBUG "GMAC: disable RX SF mode (threshold %d)\n",

			 rxmode);

		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);

		csr6 &= ~DMA_CONTROL_RSF;

		csr6 &= DMA_CONTROL_TC_RX_MASK;

		if (rxmode <= 32)

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

+0 −4
Original line number Diff line number Diff line
@@ -135,10 +135,6 @@ static void dwmac100_set_filter(struct net_device *dev, int id) 
	}



	writel(value, ioaddr + MAC_CONTROL);



	CHIP_DBG(KERN_INFO "%s: Filter: 0x%08x Hash: HI 0x%08x, LO 0x%08x\n",

		 __func__, readl(ioaddr + MAC_CONTROL),

		 readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));

}



static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -90,14 +90,14 @@ static void dwmac100_dump_dma_regs(void __iomem *ioaddr) 
{

	int i;



	CHIP_DBG(KERN_DEBUG "DWMAC 100 DMA CSR\n");

	pr_debug("DWMAC 100 DMA CSR\n");

	for (i = 0; i < 9; i++)

		pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,

			 (DMA_BUS_MODE + i * 4),

			 readl(ioaddr + DMA_BUS_MODE + i * 4));

	CHIP_DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",

		 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));

	CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",



	pr_debug("\tCSR20 (0x%x): 0x%08x, CSR21 (0x%x): 0x%08x\n",

		 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR),

		 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));

}

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