Commit 83d00287 authored Nov 19, 2020 by Eugen Hristev Committed by Stephen Boyd Dec 19, 2020

clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT



Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com


Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 3d86ee17

drivers/clk/at91/sama7g5.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -117,7 +117,8 @@ static const struct {
		.p = "cpupll_fracck",
		.l = &pll_layout_divpmc,
		.t = PLL_TYPE_DIV,
		.c = 1, },
		.c = 1,
		.eid = PMC_CPUPLL, },
		},

		[PLL_ID_SYS] = {
		@@ -131,7 +132,8 @@ static const struct {
		.p = "syspll_fracck",
		.l = &pll_layout_divpmc,
		.t = PLL_TYPE_DIV,
		.c = 1, },
		.c = 1,
		.eid = PMC_SYSPLL, },
		},

		[PLL_ID_DDR] = {

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