Commit 83cf5fae authored by Ram Chandra Jangir's avatar Ram Chandra Jangir Committed by Linus Walleij
Browse files

pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits 



GPIO_PULL bits configurations in TLMM_GPIO_CFG register
differs for IPQ40xx from rest of the other qcom SoCs.
As it does not support the keeper state and therefore can't
support bias-bus-hold property.

This patch adds a pull_no_keeper setting which configures the
msm_gpio_pull bits for ipq40xx. This is required to fix the
proper configurations of gpio-pull bits for nand pins mux.

IPQ40xx SoC:
2'b10: Internal pull up enable.
2'b11: Unsupport

For other SoC's:
2'b10: Keeper
2'b11: Pull-Up

Note: Due to pull_no_keeper length, all kerneldoc entries
in the msm_pinctrl_soc_data struct had to be realigned.

Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarRam Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: default avatarChristian Lamparter <chunkeey@googlemail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 77a65959

drivers/pinctrl/qcom/pinctrl-ipq4019.c

+1 −0
Original line number Diff line number Diff line
@@ -706,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = { 
	.groups = ipq4019_groups,

	.ngroups = ARRAY_SIZE(ipq4019_groups),

	.ngpios = 100,

	.pull_no_keeper = true,

};



static int ipq4019_pinctrl_probe(struct platform_device *pdev)

drivers/pinctrl/qcom/pinctrl-msm.c

+19 −6
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, 
#define MSM_NO_PULL		0

#define MSM_PULL_DOWN		1

#define MSM_KEEPER		2

#define MSM_PULL_UP_NO_KEEPER	2

#define MSM_PULL_UP		3



static unsigned msm_regval_to_drive(u32 val)
@@ -243,9 +244,15 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, 
		arg = arg == MSM_PULL_DOWN;

		break;

	case PIN_CONFIG_BIAS_BUS_HOLD:

		if (pctrl->soc->pull_no_keeper)

			return -ENOTSUPP;



		arg = arg == MSM_KEEPER;

		break;

	case PIN_CONFIG_BIAS_PULL_UP:

		if (pctrl->soc->pull_no_keeper)

			arg = arg == MSM_PULL_UP_NO_KEEPER;

		else

			arg = arg == MSM_PULL_UP;

		break;

	case PIN_CONFIG_DRIVE_STRENGTH:
@@ -309,9 +316,15 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, 
			arg = MSM_PULL_DOWN;

			break;

		case PIN_CONFIG_BIAS_BUS_HOLD:

			if (pctrl->soc->pull_no_keeper)

				return -ENOTSUPP;



			arg = MSM_KEEPER;

			break;

		case PIN_CONFIG_BIAS_PULL_UP:

			if (pctrl->soc->pull_no_keeper)

				arg = MSM_PULL_UP_NO_KEEPER;

			else

				arg = MSM_PULL_UP;

			break;

		case PIN_CONFIG_DRIVE_STRENGTH:

drivers/pinctrl/qcom/pinctrl-msm.h

+9 −7
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ struct msm_pingroup { 
 * @groups:	    An array describing all pin groups the pin SoC supports.

 * @ngroups:	    The numbmer of entries in @groups.

 * @ngpio:	    The number of pingroups the driver should expose as GPIOs.

 * @pull_no_keeper: The SoC does not support keeper bias.

 */

struct msm_pinctrl_soc_data {

	const struct pinctrl_pin_desc *pins;
@@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data { 
	const struct msm_pingroup *groups;

	unsigned ngroups;

	unsigned ngpios;

	bool pull_no_keeper;

};



int msm_pinctrl_probe(struct platform_device *pdev,

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