Commit 83a3545d authored by Marcin Wojtas's avatar Marcin Wojtas Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: add SMMU support



Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.

Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarTomasz Nowicki <tn@semihalf.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent b3a9e3b9
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+28 −0
Original line number Diff line number Diff line
@@ -14,3 +14,31 @@
	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
		     "marvell,armada-ap806";
};

&smmu {
	status = "okay";
};

&cp0_pcie0 {
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

&cp0_sata0 {
	iommus = <&smmu 0x444>;
};

&cp0_sdhci0 {
	iommus = <&smmu 0x445>;
};

&cp0_usb3_0 {
	iommus = <&smmu 0x440>;
};

&cp0_usb3_1 {
	iommus = <&smmu 0x441>;
};
+40 −0
Original line number Diff line number Diff line
@@ -15,6 +15,18 @@
		     "marvell,armada-ap806";
};

&smmu {
	status = "okay";
};

&cp0_pcie0 {
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
 * in CP master is not connected (by package) to the oscillator. So
 * disable it. However, the RTC clock in CP slave is connected to the
@@ -23,3 +35,31 @@
&cp0_rtc {
	status = "disabled";
};

&cp0_sata0 {
	iommus = <&smmu 0x444>;
};

&cp0_sdhci0 {
	iommus = <&smmu 0x445>;
};

&cp0_usb3_0 {
	iommus = <&smmu 0x440>;
};

&cp0_usb3_1 {
	iommus = <&smmu 0x441>;
};

&cp1_sata0 {
	iommus = <&smmu 0x454>;
};

&cp1_usb3_0 {
	iommus = <&smmu 0x450>;
};

&cp1_usb3_1 {
	iommus = <&smmu 0x451>;
};
+18 −0
Original line number Diff line number Diff line
@@ -56,6 +56,24 @@
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			smmu: iommu@5000000 {
				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
				reg = <0x100000 0x100000>;
				dma-coherent;
				#iommu-cells = <1>;
				#global-interrupts = <1>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;