Commit 839c291d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'juno-updates-5.1' of... 

Merge tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt

ARMv8 Juno/fast models updates for v5.1

1. Support for Fixed Virtual Platforms(FVP) Base RevC model to enable
   development of software around the new features available

2. Addition of dynamic-power-coefficient information for CPUs on Juno

3. Miscellaneous changes like re-ordering device nodes, using existing
   macros for GIC flags in interrupt-maps and using list instead of
   tuple(which is wrong but works as number of interrupt cells is 1)
   for mmci interrupts

* tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux

:
  arm64: dts: juno: Add cpu dynamic-power-coefficient information
  arm64: dts: fast models: Add DTS fo Base RevC FVP
  arm64: dts: juno/fast models: sort couple of device nodes
  arm64: dts: models: use list instead of tuple for mmci interrupts
  arm64: dts: juno/fast models: using GIC macros instead of hardcoded values

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0d29492e 4daa001a

arch/arm64/boot/dts/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \ 
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb

arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -14,6 +14,6 @@ 
		      <0x0 0x2c002000 0 0x2000>,

		      <0x0 0x2c004000 0 0x2000>,

		      <0x0 0x2c006000 0 0x2000>;

		interrupts = <1 9 0xf04>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};

};

arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
			<0x0 0x2c000000 0x0 0x2000>,

			<0x0 0x2c010000 0x0 0x2000>,

			<0x0 0x2c02f000 0x0 0x2000>;

		interrupts = <1 9 4>;

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		its: its@2f020000 {

			compatible = "arm,gic-v3-its";

arch/arm64/boot/dts/arm/foundation-v8.dtsi

+54 −52
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 


/dts-v1/;



#include <dt-bindings/interrupt-controller/arm-gic.h>



/memreserve/ 0x80000000 0x00010000;



/ {
@@ -67,26 +69,26 @@ 


	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 13 0xf08>,

			     <1 14 0xf08>,

			     <1 11 0xf08>,

			     <1 10 0xf08>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <100000000>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <0 60 4>,

			     <0 61 4>,

			     <0 62 4>,

			     <0 63 4>;

		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

	};



	watchdog@2a440000 {

		compatible = "arm,sbsa-gwdt";

		reg = <0x0 0x2a440000 0 0x1000>,

			<0x0 0x2a450000 0 0x1000>;

		interrupts = <0 27 4>;

		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

		timeout-sec = <30>;

	};
@@ -105,49 +107,49 @@ 


		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0 0 0  0 4>,

				<0 0  1 &gic 0 0 0  1 4>,

				<0 0  2 &gic 0 0 0  2 4>,

				<0 0  3 &gic 0 0 0  3 4>,

				<0 0  4 &gic 0 0 0  4 4>,

				<0 0  5 &gic 0 0 0  5 4>,

				<0 0  6 &gic 0 0 0  6 4>,

				<0 0  7 &gic 0 0 0  7 4>,

				<0 0  8 &gic 0 0 0  8 4>,

				<0 0  9 &gic 0 0 0  9 4>,

				<0 0 10 &gic 0 0 0 10 4>,

				<0 0 11 &gic 0 0 0 11 4>,

				<0 0 12 &gic 0 0 0 12 4>,

				<0 0 13 &gic 0 0 0 13 4>,

				<0 0 14 &gic 0 0 0 14 4>,

				<0 0 15 &gic 0 0 0 15 4>,

				<0 0 16 &gic 0 0 0 16 4>,

				<0 0 17 &gic 0 0 0 17 4>,

				<0 0 18 &gic 0 0 0 18 4>,

				<0 0 19 &gic 0 0 0 19 4>,

				<0 0 20 &gic 0 0 0 20 4>,

				<0 0 21 &gic 0 0 0 21 4>,

				<0 0 22 &gic 0 0 0 22 4>,

				<0 0 23 &gic 0 0 0 23 4>,

				<0 0 24 &gic 0 0 0 24 4>,

				<0 0 25 &gic 0 0 0 25 4>,

				<0 0 26 &gic 0 0 0 26 4>,

				<0 0 27 &gic 0 0 0 27 4>,

				<0 0 28 &gic 0 0 0 28 4>,

				<0 0 29 &gic 0 0 0 29 4>,

				<0 0 30 &gic 0 0 0 30 4>,

				<0 0 31 &gic 0 0 0 31 4>,

				<0 0 32 &gic 0 0 0 32 4>,

				<0 0 33 &gic 0 0 0 33 4>,

				<0 0 34 &gic 0 0 0 34 4>,

				<0 0 35 &gic 0 0 0 35 4>,

				<0 0 36 &gic 0 0 0 36 4>,

				<0 0 37 &gic 0 0 0 37 4>,

				<0 0 38 &gic 0 0 0 38 4>,

				<0 0 39 &gic 0 0 0 39 4>,

				<0 0 40 &gic 0 0 0 40 4>,

				<0 0 41 &gic 0 0 0 41 4>,

				<0 0 42 &gic 0 0 0 42 4>;

		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  1 &gic 0 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  2 &gic 0 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  3 &gic 0 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  4 &gic 0 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  5 &gic 0 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  6 &gic 0 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  7 &gic 0 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  8 &gic 0 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  9 &gic 0 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;



		ethernet@2,02000000 {

			compatible = "smsc,lan91c111";

arch/arm64/boot/dts/arm/fvp-base-revc.dts

0 → 100644
+277 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * ARM Ltd. Fast Models

 *

 * Architecture Envelope Model (AEM) ARMv8-A

 * ARMAEMv8AMPCT

 *

 * FVP Base RevC

 */



/dts-v1/;



#include <dt-bindings/interrupt-controller/arm-gic.h>



/memreserve/ 0x80000000 0x00010000;



#include "rtsm_ve-motherboard.dtsi"

#include "rtsm_ve-motherboard-rs2.dtsi"



/ {

	model = "FVP Base RevC";

	compatible = "arm,fvp-base-revc", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	aliases {

		serial0 = &v2m_serial0;

		serial1 = &v2m_serial1;

		serial2 = &v2m_serial2;

		serial3 = &v2m_serial3;

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x000>;

			enable-method = "psci";

		};

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

		};

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

		};

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

		};

		cpu4: cpu@10000 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10000>;

			enable-method = "psci";

		};

		cpu5: cpu@10100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10100>;

			enable-method = "psci";

		};

		cpu6: cpu@10200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10200>;

			enable-method = "psci";

		};

		cpu7: cpu@10300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10300>;

			enable-method = "psci";

		};

	};



	memory@80000000 {

		device_type = "memory";

		reg = <0x00000000 0x80000000 0 0x80000000>,

		      <0x00000008 0x80000000 0 0x80000000>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		/* Chipselect 2,00000000 is physically at 0x18000000 */

		vram: vram@18000000 {

			/* 8 MB of designated video RAM */

			compatible = "shared-dma-pool";

			reg = <0x00000000 0x18000000 0 0x00800000>;

			no-map;

		};

	};



	gic: interrupt-controller@2f000000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		interrupt-controller;

		reg = <0x0 0x2f000000 0 0x10000>,	// GICD

		      <0x0 0x2f100000 0 0x200000>,	// GICR

		      <0x0 0x2c000000 0 0x2000>,	// GICC

		      <0x0 0x2c010000 0 0x2000>,	// GICH

		      <0x0 0x2c02f000 0 0x2000>;	// GICV

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		its: its@2f020000 {

			#msi-cells = <1>;

			compatible = "arm,gic-v3-its";

			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS

			msi-controller;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};



	spe-pmu {

		compatible = "arm,statistical-profiling-extension-v1";

		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;

	};



	pci: pci@40000000 {

		#address-cells = <0x3>;

		#size-cells = <0x2>;

		#interrupt-cells = <0x1>;

		compatible = "pci-host-ecam-generic";

		device_type = "pci";

		bus-range = <0x0 0x1>;

		reg = <0x0 0x40000000 0x0 0x10000000>;

		ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;

		interrupt-map = <0 0 0 1 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 2 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 3 &gic GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 0 4 &gic GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-map-mask = <0x0 0x0 0x0 0x7>;

		msi-map = <0x0 &its 0x0 0x10000>;

		iommu-map = <0x0 &smmu 0x0 0x10000>;



		dma-coherent;

	};



	smmu: smmu@2b400000 {

		compatible = "arm,smmu-v3";

		reg = <0x0 0x2b400000 0x0 0x100000>;

		interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,

			     <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";

		dma-coherent;

		#iommu-cells = <1>;

		msi-parent = <&its 0x10000>;

	};



	panel {

		compatible = "arm,rtsm-display", "panel-dpi";

		port {

			panel_in: endpoint {

				remote-endpoint = <&clcd_pads>;

			};

		};



	       panel-timing {

		       clock-frequency = <63500127>;

		       hactive = <1024>;

		       hback-porch = <152>;

		       hfront-porch = <48>;

		       hsync-len = <104>;

		       vactive = <768>;

		       vback-porch = <23>;

		       vfront-porch = <3>;

		       vsync-len = <4>;

	       };

	};



	smb@8000000 {

		compatible = "simple-bus";



		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0 0x08000000 0x04000000>,

			 <1 0 0 0x14000000 0x04000000>,

			 <2 0 0 0x18000000 0x04000000>,

			 <3 0 0 0x1c000000 0x04000000>,

			 <4 0 0 0x0c000000 0x04000000>,

			 <5 0 0 0x10000000 0x04000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  1 &gic 0 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  2 &gic 0 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  3 &gic 0 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  4 &gic 0 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  5 &gic 0 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  6 &gic 0 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  7 &gic 0 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  8 &gic 0 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,

				<0 0  9 &gic 0 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

				<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;



		motherboard {

			iofpga@3,00000000 {

				clcd@1f0000 {

					max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */

				};

			};

		};

	};

};

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