Commit 83942bdd authored Feb 12, 2018 by Sylwester Nawrocki

clk: exynos5433: Extend list of available AUD_PLL output frequencies



Add one more entry to the exynos5433_aud_pll_rates table, this allows
to support audio sample rates: 48000, 96000, 192000 Hz with minimum
error. The M, P, S, K values re confirmed by the HW team.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

parent 5c797924

drivers/clk/samsung/clk-exynos5433.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -765,6 +765,7 @@ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initcons
		PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
		PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
		PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
		PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
		{ /* sentinel */ }
		};

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