Commit 82e1b12e authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/overlay: use intel_de_*() functions for register access 



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/03a907100bf86e877247df804104c50240e3b38c.1579871655.git.jani.nikula@intel.com
parent cc80e362

drivers/gpu/drm/i915/display/intel_overlay.c

+23 −22
Original line number Diff line number Diff line
@@ -204,9 +204,10 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 


	/* WA_OVERLAY_CLKGATE:alm */

	if (enable)

		I915_WRITE(DSPCLK_GATE_D, 0);

		intel_de_write(dev_priv, DSPCLK_GATE_D, 0);

	else

		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

		intel_de_write(dev_priv, DSPCLK_GATE_D,

			       OVRUNIT_CLOCK_GATE_DISABLE);



	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */

	pci_bus_read_config_byte(pdev->bus,
@@ -321,7 +322,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay, 
		flip_addr |= OFC_UPDATE;



	/* check for underruns */

	tmp = I915_READ(DOVSTA);

	tmp = intel_de_read(dev_priv, DOVSTA);

	if (tmp & (1 << 17))

		DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
@@ -456,7 +457,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 
	if (!overlay->old_vma)

		return 0;



	if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

	if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

		intel_overlay_release_old_vid_tail(overlay);

		return 0;

	}
@@ -891,7 +892,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 
static void update_pfit_vscale_ratio(struct intel_overlay *overlay)

{

	struct drm_i915_private *dev_priv = overlay->i915;

	u32 pfit_control = I915_READ(PFIT_CONTROL);

	u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);

	u32 ratio;



	/* XXX: This is not the same logic as in the xorg driver, but more in
@@ -899,12 +900,12 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 
	 */

	if (INTEL_GEN(dev_priv) >= 4) {

		/* on i965 use the PGM reg to read out the autoscaler values */

		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;

		ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;

	} else {

		if (pfit_control & VERT_AUTO_SCALE)

			ratio = I915_READ(PFIT_AUTO_RATIOS);

			ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);

		else

			ratio = I915_READ(PFIT_PGM_RATIOS);

			ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);

		ratio >>= PFIT_VERT_SCALE_SHIFT;

	}
@@ -1239,12 +1240,12 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 
		attrs->saturation = overlay->saturation;



		if (!IS_GEN(dev_priv, 2)) {

			attrs->gamma0 = I915_READ(OGAMC0);

			attrs->gamma1 = I915_READ(OGAMC1);

			attrs->gamma2 = I915_READ(OGAMC2);

			attrs->gamma3 = I915_READ(OGAMC3);

			attrs->gamma4 = I915_READ(OGAMC4);

			attrs->gamma5 = I915_READ(OGAMC5);

			attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);

			attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);

			attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);

			attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);

			attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);

			attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);

		}

	} else {

		if (attrs->brightness < -128 || attrs->brightness > 127)
@@ -1274,12 +1275,12 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 
			if (ret)

				goto out_unlock;



			I915_WRITE(OGAMC0, attrs->gamma0);

			I915_WRITE(OGAMC1, attrs->gamma1);

			I915_WRITE(OGAMC2, attrs->gamma2);

			I915_WRITE(OGAMC3, attrs->gamma3);

			I915_WRITE(OGAMC4, attrs->gamma4);

			I915_WRITE(OGAMC5, attrs->gamma5);

			intel_de_write(dev_priv, OGAMC0, attrs->gamma0);

			intel_de_write(dev_priv, OGAMC1, attrs->gamma1);

			intel_de_write(dev_priv, OGAMC2, attrs->gamma2);

			intel_de_write(dev_priv, OGAMC3, attrs->gamma3);

			intel_de_write(dev_priv, OGAMC4, attrs->gamma4);

			intel_de_write(dev_priv, OGAMC5, attrs->gamma5);

		}

	}

	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
@@ -1419,8 +1420,8 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 
	if (error == NULL)

		return NULL;



	error->dovsta = I915_READ(DOVSTA);

	error->isr = I915_READ(GEN2_ISR);

	error->dovsta = intel_de_read(dev_priv, DOVSTA);

	error->isr = intel_de_read(dev_priv, GEN2_ISR);

	error->base = overlay->flip_addr;



	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));

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