Commit 82d375d1 authored by Zhi Wang's avatar Zhi Wang Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Introduce basic vGPU life cycle management 



A vGPU represents a virtual Intel GEN hardware, which consists following
virtual resources:

- Configuration space (virtualized)
- HW registers (virtualized)
- GGTT memory space (partitioned)
- GPU page table (shadowed)
- Fence registers (partitioned)

* virtualized: fully emulated by GVT-g.
* partitioned: Only a part of the HW resource is allowed to be accessed
by VM.
* shadowed: Resource needs to be translated and shadowed before getting
applied into HW.

This patch introduces vGPU life cycle management framework, which is
responsible for creating/destroying a vGPU and preparing/free resources
related to a vGPU.

Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 579cea5f

drivers/gpu/drm/i915/gvt/Makefile

+1 −1
Original line number Diff line number Diff line 
GVT_DIR := gvt

GVT_SOURCE := gvt.o aperture_gm.o handlers.o firmware.o

GVT_SOURCE := gvt.o aperture_gm.o handlers.o firmware.o vgpu.o



ccflags-y                      += -I$(src) -I$(src)/$(GVT_DIR) -Wall

i915-y			       += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/gvt.h

+71 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#include "debug.h"

#include "hypercall.h"

#include "mmio.h"

#include "reg.h"



#define GVT_MAX_VGPU 8
@@ -77,13 +78,37 @@ struct intel_vgpu_fence { 
	u32 size;

};



struct intel_vgpu_mmio {

	void *vreg;

	void *sreg;

};



#define INTEL_GVT_MAX_CFG_SPACE_SZ 256

#define INTEL_GVT_MAX_BAR_NUM 4



struct intel_vgpu_pci_bar {

	u64 size;

	bool tracked;

};



struct intel_vgpu_cfg_space {

	unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];

	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];

};



#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)



struct intel_vgpu {

	struct intel_gvt *gvt;

	int id;

	unsigned long handle; /* vGPU handle used by hypervisor MPT modules */

	bool active;

	bool resetting;



	struct intel_vgpu_fence fence;

	struct intel_vgpu_gm gm;

	struct intel_vgpu_cfg_space cfg_space;

	struct intel_vgpu_mmio mmio;

};



struct intel_gvt_gm {
@@ -183,6 +208,52 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 
void intel_vgpu_write_fence(struct intel_vgpu *vgpu,

	u32 fence, u64 value);



/* Macros for easily accessing vGPU virtual/shadow register */

#define vgpu_vreg(vgpu, reg) \

	(*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_vreg8(vgpu, reg) \

	(*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_vreg16(vgpu, reg) \

	(*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_vreg64(vgpu, reg) \

	(*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_sreg(vgpu, reg) \

	(*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_sreg8(vgpu, reg) \

	(*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_sreg16(vgpu, reg) \

	(*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define vgpu_sreg64(vgpu, reg) \

	(*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))



#define for_each_active_vgpu(gvt, vgpu, id) \

	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \

		for_each_if(vgpu->active)



static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,

					    u32 offset, u32 val, bool low)

{

	u32 *pval;



	/* BAR offset should be 32 bits algiend */

	offset = rounddown(offset, 4);

	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);



	if (low) {

		/*

		 * only update bit 31 - bit 4,

		 * leave the bit 3 - bit 0 unchanged.

		 */

		*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));

	}

}



struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,

					 struct intel_vgpu_creation_params *

					 param);



void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);



#include "mpt.h"



#endif

drivers/gpu/drm/i915/gvt/hypercall.h

+11 −0
Original line number Diff line number Diff line
@@ -19,6 +19,15 @@ 
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 * Authors:

 *    Eddie Dong <eddie.dong@intel.com>

 *    Dexuan Cui

 *    Jike Song <jike.song@intel.com>

 *

 * Contributors:

 *    Zhi Wang <zhi.a.wang@intel.com>

 *

 */



#ifndef _GVT_HYPERCALL_H_
@@ -30,6 +39,8 @@ 
 */

struct intel_gvt_mpt {

	int (*detect_host)(void);

	int (*attach_vgpu)(void *vgpu, unsigned long *handle);

	void (*detach_vgpu)(unsigned long handle);

};



extern struct intel_gvt_mpt xengt_mpt;

drivers/gpu/drm/i915/gvt/mpt.h

+33 −0
Original line number Diff line number Diff line
@@ -19,6 +19,15 @@ 
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 * Authors:

 *    Eddie Dong <eddie.dong@intel.com>

 *    Dexuan Cui

 *    Jike Song <jike.song@intel.com>

 *

 * Contributors:

 *    Zhi Wang <zhi.a.wang@intel.com>

 *

 */



#ifndef _GVT_MPT_H_
@@ -46,4 +55,28 @@ static inline int intel_gvt_hypervisor_detect_host(void) 
	return intel_gvt_host.mpt->detect_host();

}



/**

 * intel_gvt_hypervisor_attach_vgpu - call hypervisor to initialize vGPU

 * related stuffs inside hypervisor.

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

static inline int intel_gvt_hypervisor_attach_vgpu(struct intel_vgpu *vgpu)

{

	return intel_gvt_host.mpt->attach_vgpu(vgpu, &vgpu->handle);

}



/**

 * intel_gvt_hypervisor_detach_vgpu - call hypervisor to release vGPU

 * related stuffs inside hypervisor.

 *

 * Returns:

 * Zero on success, negative error code if failed.

 */

static inline void intel_gvt_hypervisor_detach_vgpu(struct intel_vgpu *vgpu)

{

	intel_gvt_host.mpt->detach_vgpu(vgpu->handle);

}



#endif /* _GVT_MPT_H_ */

drivers/gpu/drm/i915/gvt/reg.h

0 → 100644
+33 −0
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 */



#ifndef _GVT_REG_H

#define _GVT_REG_H



#define INTEL_GVT_PCI_CLASS_VGA_OTHER   0x80



#define INTEL_GVT_PCI_GMCH_CONTROL	0x50

#define   BDW_GMCH_GMS_SHIFT		8

#define   BDW_GMCH_GMS_MASK		0xff



#endif

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