Commit 82a1402e authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Dan Williams
Browse files

dma: mv_xor: Fix mis-usage of mmio 'base' and 'high_base' registers 



Despite requesting two memory resources, called 'base' and 'high_base', the
driver uses explicitly only the former. The latter is being used implicitly
by addressing at offset +0x200, which in practice accesses high_base.

In other words, the current driver breaks if the second memory resource
is ever place at an offset different from +0x200.

This patch fixes the above by defining the registers with the offset from
high_base, and use high_base explicitly where appropriate.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent a911ddc9

drivers/dma/mv_xor.c

+2 −1
Original line number Diff line number Diff line
@@ -1035,6 +1035,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, 
	}



	mv_chan->mmr_base = xordev->xor_base;

	mv_chan->mmr_high_base = xordev->xor_high_base;

	tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)

		     mv_chan);
@@ -1093,7 +1094,7 @@ static void 
mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,

			 const struct mbus_dram_target_info *dram)

{

	void __iomem *base = xordev->xor_base;

	void __iomem *base = xordev->xor_high_base;

	u32 win_enable = 0;

	int i;

drivers/dma/mv_xor.h

+13 −12
Original line number Diff line number Diff line
@@ -34,13 +34,13 @@ 
#define XOR_OPERATION_MODE_MEMCPY	2

#define XOR_DESCRIPTOR_SWAP		BIT(14)



#define XOR_CURR_DESC(chan)	(chan->mmr_base + 0x210 + (chan->idx * 4))

#define XOR_NEXT_DESC(chan)	(chan->mmr_base + 0x200 + (chan->idx * 4))

#define XOR_BYTE_COUNT(chan)	(chan->mmr_base + 0x220 + (chan->idx * 4))

#define XOR_DEST_POINTER(chan)	(chan->mmr_base + 0x2B0 + (chan->idx * 4))

#define XOR_BLOCK_SIZE(chan)	(chan->mmr_base + 0x2C0 + (chan->idx * 4))

#define XOR_INIT_VALUE_LOW(chan)	(chan->mmr_base + 0x2E0)

#define XOR_INIT_VALUE_HIGH(chan)	(chan->mmr_base + 0x2E4)

#define XOR_CURR_DESC(chan)	(chan->mmr_high_base + 0x10 + (chan->idx * 4))

#define XOR_NEXT_DESC(chan)	(chan->mmr_high_base + 0x00 + (chan->idx * 4))

#define XOR_BYTE_COUNT(chan)	(chan->mmr_high_base + 0x20 + (chan->idx * 4))

#define XOR_DEST_POINTER(chan)	(chan->mmr_high_base + 0xB0 + (chan->idx * 4))

#define XOR_BLOCK_SIZE(chan)	(chan->mmr_high_base + 0xC0 + (chan->idx * 4))

#define XOR_INIT_VALUE_LOW(chan)	(chan->mmr_high_base + 0xE0)

#define XOR_INIT_VALUE_HIGH(chan)	(chan->mmr_high_base + 0xE4)



#define XOR_CONFIG(chan)	(chan->mmr_base + 0x10 + (chan->idx * 4))

#define XOR_ACTIVATION(chan)	(chan->mmr_base + 0x20 + (chan->idx * 4))
@@ -50,11 +50,11 @@ 
#define XOR_ERROR_ADDR(chan)	(chan->mmr_base + 0x60)

#define XOR_INTR_MASK_VALUE	0x3F5



#define WINDOW_BASE(w)		(0x250 + ((w) << 2))

#define WINDOW_SIZE(w)		(0x270 + ((w) << 2))

#define WINDOW_REMAP_HIGH(w)	(0x290 + ((w) << 2))

#define WINDOW_BAR_ENABLE(chan)	(0x240 + ((chan) << 2))

#define WINDOW_OVERRIDE_CTRL(chan)	(0x2A0 + ((chan) << 2))

#define WINDOW_BASE(w)		(0x50 + ((w) << 2))

#define WINDOW_SIZE(w)		(0x70 + ((w) << 2))

#define WINDOW_REMAP_HIGH(w)	(0x90 + ((w) << 2))

#define WINDOW_BAR_ENABLE(chan)	(0x40 + ((chan) << 2))

#define WINDOW_OVERRIDE_CTRL(chan)	(0xA0 + ((chan) << 2))



struct mv_xor_device {

	void __iomem	     *xor_base;
@@ -82,6 +82,7 @@ struct mv_xor_chan { 
	int			pending;

	spinlock_t		lock; /* protects the descriptor slot pool */

	void __iomem		*mmr_base;

	void __iomem		*mmr_high_base;

	unsigned int		idx;

	int                     irq;

	enum dma_transaction_type	current_type;

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