Commit 829e7573 authored Apr 21, 2020 by Baruch Siach Committed by David S. Miller Apr 23, 2020

net: phy: marvell10g: limit soft reset to 88x3310



The MV_V2_PORT_CTRL_SWRST bit in MV_V2_PORT_CTRL is reserved on 88E2110.
Setting SWRST on 88E2110 breaks packets transfer after interface down/up
cycle.

Fixes: 8f48c2ac ("net: marvell10g: soft-reset the PHY when coming out of low power")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 7c74b0be

drivers/net/phy/marvell10g.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -246,7 +246,8 @@ static int mv3310_power_up(struct phy_device *phydev)
		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
		MV_V2_PORT_CTRL_PWRDOWN);

		if (priv->firmware_ver < 0x00030000)
		if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 \|\|
		priv->firmware_ver < 0x00030000)
		return ret;

		return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,

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