Merge tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

The scmi node with the following properties shall be under the /firmware/ node.

- compatible : shall be "arm,scmi"

- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports

- mboxes: List of phandle and mailbox channel specifiers. It should contain

	  exactly one or two mailboxes, one for transmitting messages("tx")

	  and another optional for receiving the notifications("rx") if

	  protocol identifier for a given sub-node.

- #size-cells : should be '0' as 'reg' property doesn't have any size

	  associated with it.

- arm,smc-id : SMC id required when using smc or hvc transports

Optional properties:

Mediatek mmsys controller

============================

The Mediatek mmsys controller provides various clocks to the system.

The Mediatek mmsys system controller provides clock control, routing control,

and miscellaneous control in mmsys partition.

Required Properties:

	- "mediatek,mt8183-mmsys", "syscon"

- #clock-cells: Must be 1

The mmsys controller uses the common clk binding from

For the clock control, the mmsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

mmsys: clock-controller@14000000 {

mmsys: syscon@14000000 {

	compatible = "mediatek,mt8173-mmsys", "syscon";

	reg = <0 0x14000000 0 0x1000>;

	#clock-cells = <1>;

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 APB-bus

maintainers:

  - Serge Semin <fancer.lancer@gmail.com>

description: |

  Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect

  which routes them to the AXI-APB bridge. This interface is a single master

  multiple slaves bus in turn serializing IO accesses and routing them to the

  addressed APB slave devices. In case of any APB protocol collisions, slave

  device not responding on timeout an IRQ is raised with an erroneous address

  reported to the APB terminator (APB Errors Handler Block).

allOf:

 - $ref: /schemas/simple-bus.yaml#

properties:

  compatible:

    contains:

      const: baikal,bt1-apb

  reg:

    items:

      - description: APB EHB MMIO registers

      - description: APB MMIO region with no any device mapped

  reg-names:

    items:

      - const: ehb

      - const: nodev

  interrupts:

    maxItems: 1

  clocks:

    items:

      - description: APB reference clock

  clock-names:

    items:

      - const: pclk

  resets:

    items:

      - description: APB domain reset line

  reset-names:

    items:

      - const: prst

unevaluatedProperties: false

required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clocks

  - clock-names

examples:

  - |

    #include <dt-bindings/interrupt-controller/mips-gic.h>

    bus@1f059000 {

      compatible = "baikal,bt1-apb", "simple-bus";

      reg = <0 0x1f059000 0 0x1000>,

            <0 0x1d000000 0 0x2040000>;

      reg-names = "ehb", "nodev";

      #address-cells = <1>;

      #size-cells = <1>;

      ranges;

      interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&ccu_sys 1>;

      clock-names = "pclk";

      resets = <&ccu_sys 1>;

      reset-names = "prst";

    };

...

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 AXI-bus

maintainers:

  - Serge Semin <fancer.lancer@gmail.com>

description: |

  AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all

  high-speed peripheral IP-cores with RAM controller and with MIPS P5600

  cores. Traffic arbitration is done by means of DW AXI Interconnect (so

  called AXI Main Interconnect) routing IO requests from one block to

  another: from CPU to SoC peripherals and between some SoC peripherals

  (mostly between peripheral devices and RAM, but also between DMA and

  some peripherals). In case of any protocol error, device not responding

  an IRQ is raised and a faulty situation is reported to the AXI EHB

  (Errors Handler Block) embedded on top of the DW AXI Interconnect and

  accessible by means of the Baikal-T1 System Controller.

allOf:

 - $ref: /schemas/simple-bus.yaml#

properties:

  compatible:

    contains:

      const: baikal,bt1-axi

  reg:

    minItems: 1

    items:

      - description: Synopsys DesignWare AXI Interconnect QoS registers

      - description: AXI EHB MMIO system controller registers

  reg-names:

    minItems: 1

    items:

      - const: qos

      - const: ehb

  '#interconnect-cells':

    const: 1

  syscon:

    $ref: /schemas/types.yaml#definitions/phandle

    description: Phandle to the Baikal-T1 System Controller DT node

  interrupts:

    maxItems: 1

  clocks:

    items:

      - description: Main Interconnect uplink reference clock

  clock-names:

    items:

      - const: aclk

  resets:

    items:

      - description: Main Interconnect reset line

  reset-names:

    items:

      - const: arst

unevaluatedProperties: false

required:

  - compatible

  - reg

  - reg-names

  - syscon

  - interrupts

  - clocks

  - clock-names

examples:

  - |

    #include <dt-bindings/interrupt-controller/mips-gic.h>

    bus@1f05a000 {

      compatible = "baikal,bt1-axi", "simple-bus";

      reg = <0 0x1f05a000 0 0x1000>,

            <0 0x1f04d110 0 0x8>;

      reg-names = "qos", "ehb";

      #address-cells = <1>;

      #size-cells = <1>;

      #interconnect-cells = <1>;

      syscon = <&syscon>;

      ranges;

      interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&ccu_axi 0>;

      clock-names = "aclk";

      resets = <&ccu_axi 0>;

      reset-names = "arst";

    };

...

Binding for NVIDIA Tegra20 CPUFreq

==================================

Required properties:

- clocks: Must contain an entry for the CPU clock.

  See ../clocks/clock-bindings.txt for details.

- operating-points-v2: See ../bindings/opp/opp.txt for details.

- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.

For each opp entry in 'operating-points-v2' table:

- opp-supported-hw: Two bitfields indicating:

	On Tegra20:

	1. CPU process ID mask

	2. SoC speedo ID mask

	On Tegra30:

	1. CPU process ID mask

	2. CPU speedo ID mask

	A bitwise AND is performed against these values and if any bit

	matches, the OPP gets enabled.

- opp-microvolt: CPU voltage triplet.

Optional properties:

- cpu-supply: Phandle to the CPU power supply.

Example:

	regulators {

		cpu_reg: regulator0 {

			regulator-name = "vdd_cpu";

		};

	};

	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp@456000000 {

			clock-latency-ns = <125000>;

			opp-microvolt = <825000 825000 1125000>;

			opp-supported-hw = <0x03 0x0001>;

			opp-hz = /bits/ 64 <456000000>;

		};

		...

	};

	cpus {

		cpu@0 {

			compatible = "arm,cortex-a9";

			clocks = <&tegra_car TEGRA20_CLK_CCLK>;

			operating-points-v2 = <&cpu0_opp_table>;

			cpu-supply = <&cpu_reg>;

			#cooling-cells = <2>;

		};

	};