drm/amd/powerplay: enable backdoor smu fw loading (v2) (827440a9) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@
		#define MP0_SRAM 0x03900000
		#define MP1_Public 0x03b00000
		#define MP1_SRAM 0x03c00004
		#define MP1_SMC_SIZE 0x40000

		/* address block */
		#define smnMP1_FIRMWARE_FLAGS 0x3010024

+33 −0

Original line number	Diff line number	Diff line
		@@ -207,6 +207,39 @@ out:

		static int smu_v11_0_load_microcode(struct smu_context *smu)
		{
		struct amdgpu_device *adev = smu->adev;
		const uint32_t *src;
		const struct smc_firmware_header_v1_0 *hdr;
		uint32_t addr_start = MP1_SRAM;
		uint32_t i;
		uint32_t mp1_fw_flags;

		hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
		src = (const uint32_t *)(adev->pm.fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes));

		for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
		WREG32_PCIE(addr_start, src[i]);
		addr_start += 4;
		}

		WREG32_PCIE(MP1_Public \| (smnMP1_PUB_CTRL & 0xffffffff),
		1 & MP1_SMN_PUB_CTRL__RESET_MASK);
		WREG32_PCIE(MP1_Public \| (smnMP1_PUB_CTRL & 0xffffffff),
		1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);

		for (i = 0; i < adev->usec_timeout; i++) {
		mp1_fw_flags = RREG32_PCIE(MP1_Public \|
		(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
		MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
		break;
		udelay(1);
		}

		if (i == adev->usec_timeout)
		return -ETIME;

		return 0;
		}