Commit 8271b2ef authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Track pipe csc enable in crtc state 



Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.

v2: Rebase
v3: Allow fastboot with csc_enable changes (Maarten)
    Deal with HAS_GMCH

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
parent 5f29ab23

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -6130,7 +6130,7 @@ enum { 
#define   MCURSOR_PIPE_SELECT_SHIFT	28

#define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)

#define   MCURSOR_GAMMA_ENABLE  (1 << 26)

#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)

#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */

#define   MCURSOR_ROTATE_180	(1 << 15)

#define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)

#define _CURABASE		0x70084
@@ -6185,7 +6185,7 @@ enum { 
#define   DISPPLANE_RGBA888			(0xf << 26)

#define   DISPPLANE_STEREO_ENABLE		(1 << 25)

#define   DISPPLANE_STEREO_DISABLE		0

#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)

#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */

#define   DISPPLANE_SEL_PIPE_SHIFT		24

#define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)

#define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)

drivers/gpu/drm/i915/intel_color.c

+6 −1
Original line number Diff line number Diff line
@@ -401,6 +401,7 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) 
	 */

	if (crtc_state->gamma_enable)

		val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;

	if (crtc_state->csc_enable)

		val |= SKL_BOTTOM_COLOR_CSC_ENABLE;

	I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
@@ -668,6 +669,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state) 


	crtc_state->gamma_enable = true;



	if (INTEL_GEN(dev_priv) >= 9 ||

	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))

		crtc_state->csc_enable = true;



	/* Always allow legacy gamma LUT with no further checking. */

	if (crtc_state_is_legacy_gamma(crtc_state)) {

		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;

drivers/gpu/drm/i915/intel_display.c

+14 −4
Original line number Diff line number Diff line
@@ -3224,7 +3224,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->gamma_enable)

		dspcntr |= DISPPLANE_GAMMA_ENABLE;



	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

	if (crtc_state->csc_enable)

		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;



	if (INTEL_GEN(dev_priv) < 5)
@@ -3705,6 +3705,7 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->gamma_enable)

		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;



	if (crtc_state->csc_enable)

		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;



	return plane_ctl;
@@ -3760,6 +3761,7 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->gamma_enable)

		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;



	if (crtc_state->csc_enable)

		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;



	return plane_color_ctl;
@@ -8108,6 +8110,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 


	if (tmp & DISPPLANE_GAMMA_ENABLE)

		crtc_state->gamma_enable = true;



	if (!HAS_GMCH(dev_priv) &&

	    tmp & DISPPLANE_PIPE_CSC_ENABLE)

		crtc_state->csc_enable = true;

}



static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -9879,6 +9885,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 


		if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)

			pipe_config->gamma_enable = true;



		if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)

			pipe_config->csc_enable = true;

	} else {

		i9xx_get_pipe_color_config(pipe_config);

	}
@@ -10215,7 +10224,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->gamma_enable)

		cntl = MCURSOR_GAMMA_ENABLE;



	if (HAS_DDI(dev_priv))

	if (crtc_state->csc_enable)

		cntl |= MCURSOR_PIPE_CSC_ENABLE;



	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
@@ -12115,6 +12124,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, 


		PIPE_CONF_CHECK_X(gamma_mode);

		PIPE_CONF_CHECK_BOOL(gamma_enable);

		PIPE_CONF_CHECK_BOOL(csc_enable);

	}



	PIPE_CONF_CHECK_BOOL(double_wide);

drivers/gpu/drm/i915/intel_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -963,6 +963,9 @@ struct intel_crtc_state { 
	/* enable pipe gamma? */

	bool gamma_enable;



	/* enable pipe csc? */

	bool csc_enable;



	/* Display Stream compression state */

	struct {

		bool compression_enable;

drivers/gpu/drm/i915/intel_sprite.c

+4 −2
Original line number Diff line number Diff line
@@ -921,13 +921,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane, 


static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	u32 sprctl = 0;



	if (crtc_state->gamma_enable)

		sprctl |= SPRITE_GAMMA_ENABLE;



	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

	if (crtc_state->csc_enable)

		sprctl |= SPRITE_PIPE_CSC_ENABLE;



	return sprctl;
@@ -1118,6 +1117,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->gamma_enable)

		dvscntr |= DVS_GAMMA_ENABLE;



	if (crtc_state->csc_enable)

		dvscntr |= DVS_PIPE_CSC_ENABLE;



	return dvscntr;

}

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