Commit 825da4d9 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn:Correct VCN cache window definition 



Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b17c5249

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+1 −2
Original line number Diff line number Diff line
@@ -121,8 +121,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
			version_major, version_minor, family_id);

	}



	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE

		  +  AMDGPU_VCN_SESSION_SIZE * 40;

	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;

	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)

		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);

	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+3 −3
Original line number Diff line number Diff line
@@ -24,9 +24,9 @@ 
#ifndef __AMDGPU_VCN_H__

#define __AMDGPU_VCN_H__



#define AMDGPU_VCN_STACK_SIZE		(200*1024)

#define AMDGPU_VCN_HEAP_SIZE		(256*1024)

#define AMDGPU_VCN_SESSION_SIZE		(50*1024)

#define AMDGPU_VCN_STACK_SIZE		(128*1024)

#define AMDGPU_VCN_CONTEXT_SIZE	(512*1024)



#define AMDGPU_VCN_FIRMWARE_OFFSET	256

#define AMDGPU_VCN_MAX_ENC_RINGS	3

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+14 −10
Original line number Diff line number Diff line
@@ -278,6 +278,7 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 
	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);

	uint32_t offset;



	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

			     (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
@@ -297,20 +298,21 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 


	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);



	/* cache window 1: stack */

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

		     lower_32_bits(adev->vcn.gpu_addr + offset));

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

		     upper_32_bits(adev->vcn.gpu_addr + offset));

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);



	/* cache window 2: context */

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));

		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));

		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,

			AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));

	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);



	WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);
@@ -325,6 +327,7 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 
	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);

	uint32_t offset;



	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

			     (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
@@ -347,24 +350,25 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 


	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);



	/* cache window 1: stack */

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

		     lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

		     upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,

			     0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE,

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,

			     0xFFFFFFFF, 0);



	/* cache window 2: context */

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE),

		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

			     0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE),

		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

			     0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,

			AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40),

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,

			     0xFFFFFFFF, 0);



	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,

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