Commit 8226f113 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - added support for MIPSr5 and P5600 cores

 - converted Loongson PCI driver into a PCI host driver using the
   generic PCI framework

 - added emulation of CPUCFG command for Loogonson64 cpus

 - removed of LASAT, PMC MSP71xx and NEC MARKEINS/EMMA

 - ioremap cleanup

 - fix for a race between two threads faulting the same page

 - various cleanups and fixes

* tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (143 commits)
  MIPS: ralink: drop ralink_clk_init for mt7621
  MIPS: ralink: bootrom: mark a function as __init to save some memory
  MIPS: Loongson64: Reorder CPUCFG model match arms
  MIPS: Expose Loongson CPUCFG availability via HWCAP
  MIPS: Loongson64: Guard against future cores without CPUCFG
  MIPS: Fix build warning about "PTR_STR" redefinition
  MIPS: Loongson64: Remove not used pci.c
  MIPS: Loongson64: Define PCI_IOBASE
  MIPS: CPU_LOONGSON2EF need software to maintain cache consistency
  MIPS: DTS: Fix build errors used with various configs
  MIPS: Loongson64: select NO_EXCEPT_FILL
  MIPS: Fix IRQ tracing when call handle_fpe() and handle_msa_fpe()
  MIPS: mm: add page valid judgement in function pte_modify
  mm/memory.c: Add memory read privilege on page fault handling
  mm/memory.c: Update local TLB if PTE entry exists
  MIPS: Do not flush tlb page when updating PTE entry
  MIPS: ingenic: Default to a generic board
  MIPS: ingenic: Add support for GCW Zero prototype
  MIPS: ingenic: DTS: Add memory info of GCW Zero
  MIPS: Loongson64: Switch to generic PCI driver
  ...
parents e8f4abf8 9bd0bd26

Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml

0 → 100644
+40 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Loongson RS780E PCH ACPI Controller



maintainers:

  - Jiaxun Yang <jiaxun.yang@flygoat.com>



description: |

  This controller can be found in Loongson-3 systems with RS780E PCH.



properties:

  compatible:

    const: loongson,rs780e-acpi



  reg:

    maxItems: 1



required:

  - compatible

  - reg



examples:

  - |

    isa@0 {

      compatible = "isa";

      #address-cells = <2>;

      #size-cells = <1>;

      ranges = <1 0 0 0x1000>;



      acpi@800 {

        compatible = "loongson,rs780e-acpi";

        reg = <1 0x800 0x100>;

      };

    };



...

Documentation/devicetree/bindings/pci/loongson.yaml

0 → 100644
+62 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/loongson.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson PCI Host Controller



maintainers:

  - Jiaxun Yang <jiaxun.yang@flygoat.com>



description: |+

  PCI host controller found on Loongson PCHs and SoCs.



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    oneOf:

      - const: loongson,ls2k-pci

      - const: loongson,ls7a-pci

      - const: loongson,rs780e-pci



  reg:

    minItems: 1

    maxItems: 2

    items:

      - description: CFG0 standard config space register

      - description: CFG1 extended config space register



  ranges:

    minItems: 1

    maxItems: 3





required:

  - compatible

  - reg

  - ranges



examples:

  - |



    bus {

        #address-cells = <2>;

        #size-cells = <2>;

        pcie@1a000000 {

            compatible = "loongson,rs780e-pci";

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;



            // CPU_PHYSICAL(2)  SIZE(2)

            reg = <0x0 0x1a000000  0x0 0x2000000>;



            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)

            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,

                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;

        };

    };

...

arch/mips/Kbuild

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ obj-y := $(platform-y) 


# make clean traverses $(obj-) without having included .config, so

# everything ends up here

obj- := $(platform-)

obj- := $(platform-y)



# mips object files

# The object files are linked as core-y files would be linked

arch/mips/Kbuild.platforms

+39 −37
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# All platforms listed in alphabetic order



platforms += alchemy

platforms += ar7

platforms += ath25

platforms += ath79

platforms += bcm47xx

platforms += bcm63xx

platforms += bmips

platforms += cavium-octeon

platforms += cobalt

platforms += dec

platforms += emma

platforms += generic

platforms += jazz

platforms += jz4740

platforms += lantiq

platforms += lasat

platforms += loongson2ef

platforms += loongson32

platforms += loongson64

platforms += mti-malta

platforms += netlogic

platforms += paravirt

platforms += pic32

platforms += pistachio

platforms += pmcs-msp71xx

platforms += pnx833x

platforms += ralink

platforms += rb532

platforms += sgi-ip22

platforms += sgi-ip27

platforms += sgi-ip30

platforms += sgi-ip32

platforms += sibyte

platforms += sni

platforms += txx9

platforms += vr41xx

platform-$(CONFIG_MIPS_ALCHEMY)		+= alchemy/

platform-$(CONFIG_AR7)			+= ar7/

platform-$(CONFIG_ATH25)		+= ath25/

platform-$(CONFIG_ATH79)		+= ath79/

platform-$(CONFIG_BCM47XX)		+= bcm47xx/

platform-$(CONFIG_BCM63XX)		+= bcm63xx/

platform-$(CONFIG_BMIPS_GENERIC)	+= bmips/

platform-$(CONFIG_CAVIUM_OCTEON_SOC)	+= cavium-octeon/

platform-$(CONFIG_MIPS_COBALT)		+= cobalt/

platform-$(CONFIG_MACH_DECSTATION)	+= dec/

platform-$(CONFIG_MIPS_GENERIC)		+= generic/

platform-$(CONFIG_MACH_JAZZ)		+= jazz/

platform-$(CONFIG_MACH_INGENIC)		+= jz4740/

platform-$(CONFIG_LANTIQ)		+= lantiq/

platform-$(CONFIG_MACH_LOONGSON2EF)	+= loongson2ef/

platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/

platform-$(CONFIG_MACH_LOONGSON64)	+= loongson64/

platform-$(CONFIG_MIPS_MALTA)		+= mti-malta/

platform-$(CONFIG_NLM_COMMON)		+= netlogic/

platform-$(CONFIG_MIPS_PARAVIRT)	+= paravirt/

platform-$(CONFIG_PIC32MZDA)		+= pic32/

platform-$(CONFIG_MACH_PISTACHIO)	+= pistachio/

platform-$(CONFIG_SOC_PNX833X)		+= pnx833x/

platform-$(CONFIG_RALINK)		+= ralink/

platform-$(CONFIG_MIKROTIK_RB532)	+= rb532/

platform-$(CONFIG_SGI_IP22)		+= sgi-ip22/

platform-$(CONFIG_SGI_IP27)		+= sgi-ip27/

platform-$(CONFIG_SGI_IP28)		+= sgi-ip22/

platform-$(CONFIG_SGI_IP30)		+= sgi-ip30/

platform-$(CONFIG_SGI_IP32)		+= sgi-ip32/

platform-$(CONFIG_SIBYTE_BCM112X)	+= sibyte/

platform-$(CONFIG_SIBYTE_SB1250)	+= sibyte/

platform-$(CONFIG_SIBYTE_BCM1x55)	+= sibyte/

platform-$(CONFIG_SIBYTE_BCM1x80)	+= sibyte/

platform-$(CONFIG_SNI_RM)		+= sni/

platform-$(CONFIG_MACH_TX39XX)		+= txx9/

platform-$(CONFIG_MACH_TX49XX)		+= txx9/

platform-$(CONFIG_MACH_VR41XX)		+= vr41xx/



# include the platform specific files

include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
 
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platform-y))

arch/mips/Kconfig

+100 −74
Original line number Diff line number Diff line
@@ -92,6 +92,9 @@ config MIPS 
	select SYSCTL_EXCEPTION_TRACE

	select VIRT_TO_BUS



config MIPS_FIXUP_BIGPHYS_ADDR

	bool



menu "Machine selection"



choice
@@ -157,6 +160,7 @@ config MIPS_ALCHEMY 
	select CSRC_R4K

	select IRQ_MIPS_CPU

	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is

	select MIPS_FIXUP_BIGPHYS_ADDR if PCI

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_APM_EMULATION
@@ -427,23 +431,6 @@ config LANTIQ 
	select ARCH_HAS_RESET_CONTROLLER

	select RESET_CONTROLLER



config LASAT

	bool "LASAT Networks platforms"

	select CEVT_R4K

	select CRC32

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select HAVE_PCI

	select IRQ_MIPS_CPU

	select PCI_GT64XXX_PCI0

	select MIPS_NILE4

	select R5000_CPU_SCACHE

	select SYS_HAS_CPU_R5000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL if BROKEN

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MACH_LOONGSON32

	bool "Loongson 32-bit family of machines"

	select SYS_SUPPORTS_ZBOOT
@@ -475,8 +462,10 @@ config MACH_LOONGSON64 
	select ISA

	select I8259

	select IRQ_MIPS_CPU

	select NR_CPUS_DEFAULT_4

	select NO_EXCEPT_FILL

	select NR_CPUS_DEFAULT_64

	select USE_GENERIC_EARLY_PRINTK_8250

	select PCI_DRIVERS_GENERIC

	select SYS_HAS_CPU_LOONGSON64

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_SMP
@@ -593,13 +582,6 @@ config MACH_PIC32 
	  Microchip PIC32 is a family of general-purpose 32 bit MIPS core

	  microcontrollers.



config NEC_MARKEINS

	bool "NEC EMMA2RH Mark-eins board"

	select SOC_EMMA2RH

	select HAVE_PCI

	help

	  This enables support for the NEC Electronics Mark-eins boards.



config MACH_VR41XX

	bool "NEC VR4100 series based machines"

	select CEVT_R4K
@@ -621,30 +603,6 @@ config NXP_STB225 
	help

	  Support for NXP Semiconductors STB225 Development Board.



config PMC_MSP

	bool "PMC-Sierra MSP chipsets"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select SWAP_IO_SPACE

	select NO_EXCEPT_FILL

	select BOOT_RAW

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MIPS16

	select IRQ_MIPS_CPU

	select SERIAL_8250

	select SERIAL_8250_CONSOLE

	select USB_EHCI_BIG_ENDIAN_MMIO

	select USB_EHCI_BIG_ENDIAN_DESC

	help

	  This adds support for the PMC-Sierra family of Multi-Service

	  Processor System-On-A-Chips.  These parts include a number

	  of integrated peripherals, interfaces and DSPs in addition to

	  a variety of MIPS cores.



config RALINK

	bool "Ralink based machines"

	select CEVT_R4K
@@ -1087,10 +1045,8 @@ source "arch/mips/generic/Kconfig" 
source "arch/mips/jazz/Kconfig"

source "arch/mips/jz4740/Kconfig"

source "arch/mips/lantiq/Kconfig"

source "arch/mips/lasat/Kconfig"

source "arch/mips/pic32/Kconfig"

source "arch/mips/pistachio/Kconfig"

source "arch/mips/pmcs-msp71xx/Kconfig"

source "arch/mips/ralink/Kconfig"

source "arch/mips/sgi-ip27/Kconfig"

source "arch/mips/sibyte/Kconfig"
@@ -1154,6 +1110,7 @@ config CSRC_IOASIC 
	bool



config CSRC_R4K

	select CLOCKSOURCE_WATCHDOG if CPU_FREQ

	bool



config CSRC_SB1250
@@ -1211,9 +1168,6 @@ config MIPS_BONITO64 
config MIPS_MSC

	bool



config MIPS_NILE4

	bool



config SYNC_R4K

	bool
@@ -1334,18 +1288,6 @@ config PCI_XTALK_BRIDGE 
config NO_EXCEPT_FILL

	bool



config SOC_EMMA2RH

	bool

	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select IRQ_MIPS_CPU

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_R5500

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN



config SOC_PNX833X

	bool

	select CEVT_R4K
@@ -1419,9 +1361,6 @@ config MIPS_L1_CACHE_SHIFT 
	default "4" if MIPS_L1_CACHE_SHIFT_4

	default "5"



config HAVE_STD_PC_SERIAL_PORT

	bool



config ARC_CMDLINE_ONLY

	bool
@@ -1504,6 +1443,18 @@ config CPU_LOONGSON3_WORKAROUNDS 


	  If unsure, please say Y.



config CPU_LOONGSON3_CPUCFG_EMULATION

	bool "Emulate the CPUCFG instruction on older Loongson cores"

	default y

	depends on CPU_LOONGSON64

	help

	  Loongson-3A R4 and newer have the CPUCFG instruction available for

	  userland to query CPU capabilities, much like CPUID on x86. This

	  option provides emulation of the instruction on older Loongson

	  cores, back to Loongson-3A1000.



	  If unsure, please say Y.



config CPU_LOONGSON2E

	bool "Loongson 2E"

	depends on SYS_HAS_CPU_LOONGSON2E
@@ -1580,6 +1531,21 @@ config CPU_MIPS32_R2 
	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.



config CPU_MIPS32_R5

	bool "MIPS32 Release 5"

	depends on SYS_HAS_CPU_MIPS32_R5

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select HAVE_KVM

	select MIPS_O32_FP64_SUPPORT

	help

	  Choose this option to build a kernel for release 5 or later of the

	  MIPS32 architecture.  New MIPS processors, starting with the Warrior

	  family, are based on a MIPS32r5 processor. If you own an older

	  processor, you probably need to select MIPS32r1 or MIPS32r2 instead.



config CPU_MIPS32_R6

	bool "MIPS32 Release 6"

	depends on SYS_HAS_CPU_MIPS32_R6
@@ -1632,6 +1598,23 @@ config CPU_MIPS64_R2 
	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.



config CPU_MIPS64_R5

	bool "MIPS64 Release 5"

	depends on SYS_HAS_CPU_MIPS64_R5

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_SUPPORTS_MSA

	select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32

	select HAVE_KVM

	help

	  Choose this option to build a kernel for release 5 or later of the

	  MIPS64 architecture.  This is a intermediate MIPS architecture

	  release partly implementing release 6 features. Though there is no

	  any hardware known to be based on this release.



config CPU_MIPS64_R6

	bool "MIPS64 Release 6"

	depends on SYS_HAS_CPU_MIPS64_R6
@@ -1650,6 +1633,28 @@ config CPU_MIPS64_R6 
	  family, are based on a MIPS64r6 processor. If you own an older

	  processor, you probably need to select MIPS64r1 or MIPS64r2 instead.



config CPU_P5600

	bool "MIPS Warrior P5600"

	depends on SYS_HAS_CPU_P5600

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select CPU_SUPPORTS_UNCACHED_ACCELERATED

	select CPU_SUPPORTS_CPUFREQ

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select HAVE_KVM

	select MIPS_O32_FP64_SUPPORT

	help

	  Choose this option to build a kernel for MIPS Warrior P5600 CPU.

	  It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,

	  MMU with two-levels TLB, UCA, MSA, MDU core level features and system

	  level features like up to six P5600 calculation cores, CM2 with L2

	  cache, IOCU/IOMMU (though might be unused depending on the system-

	  specific IP core configuration), GIC, CPC, virtualisation module,

	  eJTAG and PDtrace.



config CPU_R3000

	bool "R3000"

	depends on SYS_HAS_CPU_R3000
@@ -1826,7 +1831,8 @@ endchoice 
config CPU_MIPS32_3_5_FEATURES

	bool "MIPS32 Release 3.5 Features"

	depends on SYS_HAS_CPU_MIPS32_R3_5

	depends on CPU_MIPS32_R2 || CPU_MIPS32_R6

	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \

		   CPU_P5600

	help

	  Choose this option to build a kernel for release 2 or later of the

	  MIPS32 architecture including features from the 3.5 release such as
@@ -1846,7 +1852,7 @@ config CPU_MIPS32_3_5_EVA 
config CPU_MIPS32_R5_FEATURES

	bool "MIPS32 Release 5 Features"

	depends on SYS_HAS_CPU_MIPS32_R5

	depends on CPU_MIPS32_R2

	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600

	help

	  Choose this option to build a kernel for release 2 or later of the

	  MIPS32 architecture including features from release 5 such as
@@ -2001,6 +2007,10 @@ config SYS_HAS_CPU_MIPS64_R6 
	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_P5600

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_R3000

	bool
@@ -2084,11 +2094,13 @@ endmenu 
#

config CPU_MIPS32

	bool

	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6

	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \

		     CPU_MIPS32_R6 || CPU_P5600



config CPU_MIPS64

	bool

	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6

	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \

		     CPU_MIPS64_R6



#

# These indicate the revision of the architecture
@@ -2104,6 +2116,13 @@ config CPU_MIPSR2 
	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN

	select MIPS_SPRAM



config CPU_MIPSR5

	bool

	default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600

	select CPU_HAS_RIXI

	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN

	select MIPS_SPRAM



config CPU_MIPSR6

	bool

	default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
@@ -2118,6 +2137,7 @@ config TARGET_ISA_REV 
	int

	default 1 if CPU_MIPSR1

	default 2 if CPU_MIPSR2

	default 5 if CPU_MIPSR5

	default 6 if CPU_MIPSR6

	default 0

	help
@@ -2707,7 +2727,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK 


config RELOCATABLE

	bool "Relocatable kernel"

	depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)

	depends on SYS_SUPPORTS_RELOCATABLE

	depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \

		   CPU_MIPS32_R5 || CPU_MIPS64_R5 || \

		   CPU_MIPS32_R6 || CPU_MIPS64_R6 || \

		   CPU_P5600 || CAVIUM_OCTEON_SOC

	help

	  This builds a kernel image that retains relocation information

	  so it can be loaded someplace besides the default 1MB.
@@ -3275,3 +3299,5 @@ endmenu 
source "drivers/firmware/Kconfig"



source "arch/mips/kvm/Kconfig"



source "arch/mips/vdso/Kconfig"

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