Commit 82054678 authored by Martin Leung's avatar Martin Leung Committed by Alex Deucher
Browse files

drm/amd/display: Link training TPS1 workaround 



[Why]
Previously implemented early_cr_pattern was link level but the whole
asic should be affected.

[How]
 - change old link flag to dc level
 - new bit in dc->work_arounds set by DM

Signed-off-by: default avatarMartin Leung <martin.leung@amd.com>
Reviewed-by: default avatarJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dc326f61

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+9 −9
Original line number Diff line number Diff line
@@ -973,7 +973,7 @@ static enum link_training_result perform_clock_recovery_sequence( 
	retries_cr = 0;

	retry_count = 0;



	if (!link->wa_flags.dp_early_cr_pattern)

	if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)

		dp_set_hw_training_pattern(link, tr_pattern, offset);



	/* najeeb - The synaptics MST hub can put the LT in
@@ -1446,10 +1446,10 @@ enum link_training_result dc_link_dp_perform_link_training( 
			&link->preferred_training_settings,

			&lt_settings);



	if (link->wa_flags.dp_early_cr_pattern)

		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);



	/* 1. set link rate, lane count and spread. */

	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);

	else

		dpcd_set_link_settings(link, &lt_settings);



	if (link->preferred_training_settings.fec_enable != NULL)
@@ -1669,10 +1669,10 @@ enum link_training_result dc_link_dp_sync_lt_attempt( 
	dp_set_panel_mode(link, panel_mode);



	/* Attempt to train with given link training settings */

	if (link->wa_flags.dp_early_cr_pattern)

		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);



	/* Set link rate, lane count and spread. */

	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);

	else

		dpcd_set_link_settings(link, &lt_settings);



	/* 2. perform link training (set link training done

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -126,6 +126,7 @@ struct dc_bug_wa { 
	bool no_connect_phy_config;

	bool dedcn20_305_wa;

	bool skip_clock_update;

	bool lt_early_cr_pattern;

};



struct dc_dcc_surface_param {

drivers/gpu/drm/amd/display/dc/dc_link.h

+0 −1
Original line number Diff line number Diff line
@@ -135,7 +135,6 @@ struct dc_link { 
		bool dp_keep_receiver_powered;

		bool dp_skip_DID2;

		bool dp_skip_reset_segment;

		bool dp_early_cr_pattern;

	} wa_flags;

	struct link_mst_stream_allocation_table mst_stream_alloc_table;

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