Merge branch 'linus' into core/urgent, to merge in dependent changes

  - 'ata_qc_for_each_with_internal'

  - 'ax25_for_each'

  - 'ax25_uid_for_each'

  - '__bio_for_each_bvec'

  - 'bio_for_each_bvec'

  - 'bio_for_each_integrity_vec'

  - '__bio_for_each_segment'

  - 'bio_for_each_segment'

  - 'drm_for_each_legacy_plane'

  - 'drm_for_each_plane'

  - 'drm_for_each_plane_mask'

  - 'drm_for_each_privobj'

  - 'drm_mm_for_each_hole'

  - 'drm_mm_for_each_node'

  - 'drm_mm_for_each_node_in_range'

  - 'drm_mm_for_each_node_safe'

  - 'flow_action_for_each'

  - 'for_each_active_drhd_unit'

  - 'for_each_active_iommu'

  - 'for_each_available_child_of_node'

  - 'for_each_dss_dev'

  - 'for_each_efi_memory_desc'

  - 'for_each_efi_memory_desc_in_map'

  - 'for_each_element'

  - 'for_each_element_extid'

  - 'for_each_element_id'

  - 'for_each_endpoint_of_node'

  - 'for_each_evictable_lru'

  - 'for_each_fib6_node_rt_rcu'

  - 'for_each_net_rcu'

  - 'for_each_new_connector_in_state'

  - 'for_each_new_crtc_in_state'

  - 'for_each_new_mst_mgr_in_state'

  - 'for_each_new_plane_in_state'

  - 'for_each_new_private_obj_in_state'

  - 'for_each_node'

  - 'for_each_of_pci_range'

  - 'for_each_old_connector_in_state'

  - 'for_each_old_crtc_in_state'

  - 'for_each_old_mst_mgr_in_state'

  - 'for_each_oldnew_connector_in_state'

  - 'for_each_oldnew_crtc_in_state'

  - 'for_each_oldnew_mst_mgr_in_state'

  - 'for_each_oldnew_plane_in_state'

  - 'for_each_oldnew_plane_in_state_reverse'

  - 'for_each_oldnew_private_obj_in_state'

  - 'for_each_sg_dma_page'

  - 'for_each_sg_page'

  - 'for_each_sibling_event'

  - 'for_each_subelement'

  - 'for_each_subelement_extid'

  - 'for_each_subelement_id'

  - '__for_each_thread'

  - 'for_each_thread'

  - 'for_each_zone'

  - 'fwnode_for_each_child_node'

  - 'fwnode_graph_for_each_endpoint'

  - 'gadget_for_each_ep'

  - 'genradix_for_each'

  - 'genradix_for_each_from'

  - 'hash_for_each'

  - 'hash_for_each_possible'

  - 'hash_for_each_possible_rcu'

  - 'key_for_each'

  - 'key_for_each_safe'

  - 'klp_for_each_func'

  - 'klp_for_each_func_safe'

  - 'klp_for_each_func_static'

  - 'klp_for_each_object'

  - 'klp_for_each_object_safe'

  - 'klp_for_each_object_static'

  - 'kvm_for_each_memslot'

  - 'kvm_for_each_vcpu'

  - 'list_for_each'

  - 'media_device_for_each_intf'

  - 'media_device_for_each_link'

  - 'media_device_for_each_pad'

  - 'mp_bvec_for_each_page'

  - 'mp_bvec_for_each_segment'

  - 'nanddev_io_for_each_page'

  - 'netdev_for_each_lower_dev'

  - 'netdev_for_each_lower_private'

  - 'rht_for_each_rcu'

  - 'rht_for_each_rcu_continue'

  - '__rq_for_each_bio'

  - 'rq_for_each_bvec'

  - 'rq_for_each_segment'

  - 'scsi_for_each_prot_sg'

  - 'scsi_for_each_sg'

  - 'v4l2_m2m_for_each_src_buf_safe'

  - 'virtio_device_for_each_vq'

  - 'xa_for_each'

  - 'xa_for_each_marked'

  - 'xa_for_each_start'

  - 'xas_for_each'

  - 'xas_for_each_conflict'

  - 'xas_for_each_marked'

Morten Welinder <welinder@troll.com>

Mythri P K <mythripk@ti.com>

Nguyen Anh Quynh <aquynh@gmail.com>

Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>

Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>

Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>

Patrick Mochel <mochel@digitalimplant.org>

Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>

			 "off"		  SMT is disabled

			 "forceoff"	  SMT is force disabled. Cannot be changed.

			 "notsupported"   SMT is not supported by the CPU

			 "notimplemented" SMT runtime toggling is not

					  implemented for the architecture

			 If control status is "forceoff" or "notsupported" writes

			 are rejected.

What:		/sys/devices/system/cpu/cpu#/power/energy_perf_bias

Date:		March 2019

Contact:	linux-pm@vger.kernel.org

Description:	Intel Energy and Performance Bias Hint (EPB)

		EPB for the given CPU in a sliding scale 0 - 15, where a value

		of 0 corresponds to a hint preference for highest performance

		and a value of 15 corresponds to the maximum energy savings.

		In order to change the EPB value for the CPU, write either

		a number in the 0 - 15 sliding scale above, or one of the

		strings: "performance", "balance-performance", "normal",

		"balance-power", "power" (that represent values reflected by

		their meaning), to this attribute.

		This attribute is present for all online CPUs supporting the

		Intel EPB feature.

of the level of loading on the system.

</p><p>RCU updaters wait for normal grace periods by registering

RCU callbacks, either directly via <tt>call_rcu()</tt> and

friends (namely <tt>call_rcu_bh()</tt> and <tt>call_rcu_sched()</tt>),

RCU callbacks, either directly via <tt>call_rcu()</tt>

or indirectly via <tt>synchronize_rcu()</tt> and friends.

RCU callbacks are represented by <tt>rcu_head</tt> structures,

which are queued on <tt>rcu_data</tt> structures while they are

RCU-preempt Expedited Grace Periods</a></h2>

<p>

<tt>CONFIG_PREEMPT=y</tt> kernels implement RCU-preempt.

The overall flow of the handling of a given CPU by an RCU-preempt

expedited grace period is shown in the following diagram:

RCU-sched Expedited Grace Periods</a></h2>

<p>

<tt>CONFIG_PREEMPT=n</tt> kernels implement RCU-sched.

The overall flow of the handling of a given CPU by an RCU-sched

expedited grace period is shown in the following diagram:

<p>

As with RCU-preempt, RCU-sched's

<tt>synchronize_sched_expedited()</tt> ignores offline and

<tt>synchronize_rcu_expedited()</tt> ignores offline and

idle CPUs, again because they are in remotely detectable

quiescent states.

However, because the