Commit 8204502a authored by Dongwon Kim's avatar Dongwon Kim Committed by Daniel Vetter
Browse files

drm/i915: Do not hardcode s_max, ss_max and eu_mask for BXT 



We can calculate BXT values correctly from GFX fuse values without
hardcoding special limits.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Matthew D Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarDongwon Kim <dongwon.kim@intel.com>
Reviewed-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a2cad9df

drivers/gpu/drm/i915/i915_dma.c

+0 −11
Original line number Diff line number Diff line
@@ -631,17 +631,6 @@ static void gen9_sseu_info_init(struct drm_device *dev) 
	u32 fuse2, s_enable, ss_disable, eu_disable;

	u8 eu_mask = 0xff;



	/*

	 * BXT has a single slice. BXT also has at most 6 EU per subslice,

	 * and therefore only the lowest 6 bits of the 8-bit EU disable

	 * fields are valid.

	*/

	if (IS_BROXTON(dev)) {

		s_max = 1;

		eu_max = 6;

		eu_mask = 0x3f;

	}



	info = (struct intel_device_info *)&dev_priv->info;

	fuse2 = I915_READ(GEN8_FUSE2);

	s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>

CRA Git | Maintained and supported by SUSTech CRA and CCSE