Commit 81e911d0 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Ulf Hansson
Browse files

clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock 



The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.

This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent dc8797e3

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+2 −8
Original line number Diff line number Diff line
@@ -418,14 +418,8 @@ static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", 
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",

		       0x08c, 8, 3, 0);



/* TODO Support MMC2 clock's new timing mode. */

static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,

				  0x090,

				  0, 4,		/* M */

				  16, 2,	/* P */

				  24, 2,	/* mux */

				  BIT(31),	/* gate */

				  0);

static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,

				      0x090, 0);



static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",

		       0x090, 20, 3, 0);

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