Commit 81c9d563 authored by Saravanan Sekar's avatar Saravanan Sekar Committed by Linus Walleij
Browse files

pinctrl: actions: Add Actions Semi S700 pinctrl driver



Add pinctrl and gpio driver for Actions Semi S700 SoC. The driver
supports pinctrl, pinmux, pinconf, gpio and interrupt functionalities
through a range of registers common to both gpio driver and pinctrl driver.

Signed-off-by: default avatarParthiban Nallathambi <pn@denx.de>
Signed-off-by: default avatarSaravanan Sekar <sravanhome@gmail.com>
Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ba54e300
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+6 −0
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@@ -9,6 +9,12 @@ config PINCTRL_OWL
	help
	  Say Y here to enable Actions Semi OWL pinctrl driver

config PINCTRL_S700
	bool "Actions Semi S700 pinctrl driver"
	depends on PINCTRL_OWL
	help
	  Say Y here to enable Actions Semi S700 pinctrl driver

config PINCTRL_S900
	bool "Actions Semi S900 pinctrl driver"
	depends on PINCTRL_OWL
+1 −0
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obj-$(CONFIG_PINCTRL_OWL)	+= pinctrl-owl.o
obj-$(CONFIG_PINCTRL_S700) 	+= pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) 	+= pinctrl-s900.o
+4 −3
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@@ -739,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data)
	val = readl_relaxed(gpio_base + port->intc_msk);
	if (val == 0)
		owl_gpio_update_reg(gpio_base + port->intc_ctl,
					OWL_GPIO_CTLR_ENABLE, false);
					OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
@@ -763,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data)

	/* enable port interrupt */
	value = readl_relaxed(gpio_base + port->intc_ctl);
	value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
	value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
			<< port->shared_ctl_offset * 5);
	writel_relaxed(value, gpio_base + port->intc_ctl);

	/* enable GPIO interrupt */
@@ -801,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data)
	raw_spin_lock_irqsave(&pctrl->lock, flags);

	owl_gpio_update_reg(gpio_base + port->intc_ctl,
				OWL_GPIO_CTLR_PENDING, true);
				OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
+1912 −0

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