Commit 81c4389e authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/mdp5: Add MDP5 configuration for MSM8x36. 



This change adds MDP5 configuration for MSM8x36-based SoCs,
like MSM8936, 8939 and their APQ variants.
The configuration is based on MSM8916's, but adds some notable
features, like ad and pp blocks, along with some register
changes.

changes since v1:
- add an ad block
- add a second mixer @ 0x47000
- adjust .max_width
- write a more descriptive commit message

Signed-off-by: default avatarKonrad Dybcio <konradybcio@gmail.com>
Reviewed-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 2ef96a5b

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

+76 −0
Original line number Diff line number Diff line
@@ -342,6 +342,81 @@ static const struct mdp5_cfg_hw msm8x16_config = { 
	.max_clk = 320000000,

};



static const struct mdp5_cfg_hw msm8x36_config = {

	.name = "msm8x36",

	.mdp = {

		.count = 1,

		.base = { 0x0 },

		.caps = MDP_CAP_SMP |

			0,

	},

	.smp = {

		.mmb_count = 8,

		.mmb_size = 10240,

		.clients = {

			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,

			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,

		},

	},

	.ctl = {

		.count = 3,

		.base = { 0x01000, 0x01200, 0x01400 },

		.flush_hw_mask = 0x4003ffff,

	},

	.pipe_vig = {

		.count = 1,

		.base = { 0x04000 },

		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |

				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |

				MDP_PIPE_CAP_DECIMATION,

	},

	.pipe_rgb = {

		.count = 2,

		.base = { 0x14000, 0x16000 },

		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |

				MDP_PIPE_CAP_DECIMATION,

	},

	.pipe_dma = {

		.count = 1,

		.base = { 0x24000 },

		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,

	},

	.lm = {

		.count = 2,

		.base = { 0x44000, 0x47000 },

		.instances = {

				{ .id = 0, .pp = 0, .dspp = 0,

				  .caps = MDP_LM_CAP_DISPLAY, },

				{ .id = 1, .pp = -1, .dspp = -1,

				  .caps = MDP_LM_CAP_WB, },

				},

		.nb_stages = 8,

		.max_width = 2560,

		.max_height = 0xFFFF,

	},

	.pp = {

		.count = 1,

		.base = { 0x70000 },

	},

	.ad = {

		.count = 1,

		.base = { 0x78000 },

	},

	.dspp = {

		.count = 1,

		.base = { 0x54000 },

	},

	.intf = {

		.base = { 0x00000, 0x6a800, 0x6b000 },

		.connect = {

			[0] = INTF_DISABLED,

			[1] = INTF_DSI,

			[2] = INTF_DSI,

		},

	},

	.max_clk = 366670000,

};



static const struct mdp5_cfg_hw msm8x94_config = {

	.name = "msm8x94",

	.mdp = {
@@ -840,6 +915,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = { 
	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },

	{ .revision = 3, .config = { .hw = &apq8084_config } },

	{ .revision = 6, .config = { .hw = &msm8x16_config } },

	{ .revision = 8, .config = { .hw = &msm8x36_config } },

	{ .revision = 9, .config = { .hw = &msm8x94_config } },

	{ .revision = 7, .config = { .hw = &msm8x96_config } },

	{ .revision = 11, .config = { .hw = &msm8x76_config } },

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