Commit 81aaeaac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI fixes from Bjorn Helgaas:

 - recognize that a PCI-to-PCIe bridge originates a PCIe hierarchy, so
   we enumerate that hierarchy correctly

 - X-Gene: fix a change merged for v4.10 that broke MSI

 - Keystone: avoid reading undefined registers, which can cause
   asynchronous external aborts

 - Supermicro X8DTH-i/6/iF/6F: ignore broken _CRS that caused us to
   change (and break) existing I/O port assignments

* tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI/MSI: pci-xgene-msi: Fix CPU hotplug registration handling
  PCI: Enumerate switches below PCI-to-PCIe bridges
  x86/PCI: Ignore _CRS on Supermicro X8DTH-i/6/iF/6F
  PCI: designware: Check for iATU unroll only on platforms that use ATU
parents 2ed5e5af 4d191b1b

arch/x86/pci/acpi.c

+10 −0
Original line number Diff line number Diff line
@@ -114,6 +114,16 @@ static const struct dmi_system_id pci_crs_quirks[] __initconst = { 
			DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),

		},

	},

	/* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */

	{

		.callback = set_nouse_crs,

		.ident = "Supermicro X8DTH",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),

			DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"),

			DMI_MATCH(DMI_BIOS_VERSION, "2.0a"),

		},

	},



	/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */

	{

drivers/pci/host/pci-xgene-msi.c

+1 −1
Original line number Diff line number Diff line
@@ -517,7 +517,7 @@ static int xgene_msi_probe(struct platform_device *pdev) 


	rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",

			       xgene_msi_hwirq_alloc, NULL);

	if (rc)

	if (rc < 0)

		goto err_cpuhp;

	pci_xgene_online = rc;

	rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,

drivers/pci/host/pcie-designware.c

+5 −5
Original line number Diff line number Diff line
@@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
{

	u32 val;



	/* get iATU unroll support */

	pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);

	dev_dbg(pp->dev, "iATU unroll: %s\n",

		pp->iatu_unroll_enabled ? "enabled" : "disabled");



	/* set the number of lanes */

	val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);

	val &= ~PORT_LINK_MODE_MASK;
@@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
	 * we should not program the ATU here.

	 */

	if (!pp->ops->rd_other_conf) {

		/* get iATU unroll support */

		pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);

		dev_dbg(pp->dev, "iATU unroll: %s\n",

			pp->iatu_unroll_enabled ? "enabled" : "disabled");



		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,

					  PCIE_ATU_TYPE_MEM, pp->mem_base,

					  pp->mem_bus_addr, pp->mem_size);

drivers/pci/probe.c

+7 −5
Original line number Diff line number Diff line
@@ -1169,6 +1169,7 @@ void set_pcie_port_type(struct pci_dev *pdev) 
	pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);

	if (!pos)

		return;



	pdev->pcie_cap = pos;

	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);

	pdev->pcie_flags_reg = reg16;
@@ -1176,13 +1177,14 @@ void set_pcie_port_type(struct pci_dev *pdev) 
	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;



	/*

	 * A Root Port is always the upstream end of a Link.  No PCIe

	 * component has two Links.  Two Links are connected by a Switch

	 * that has a Port on each Link and internal logic to connect the

	 * two Ports.

	 * A Root Port or a PCI-to-PCIe bridge is always the upstream end

	 * of a Link.  No PCIe component has two Links.  Two Links are

	 * connected by a Switch that has a Port on each Link and internal

	 * logic to connect the two Ports.

	 */

	type = pci_pcie_type(pdev);

	if (type == PCI_EXP_TYPE_ROOT_PORT)

	if (type == PCI_EXP_TYPE_ROOT_PORT ||

	    type == PCI_EXP_TYPE_PCIE_BRIDGE)

		pdev->has_secondary_link = 1;

	else if (type == PCI_EXP_TYPE_UPSTREAM ||

		 type == PCI_EXP_TYPE_DOWNSTREAM) {

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