Commit 81aa844b authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

clk: imx8mm: A53 core clock no need to be critical 



'A53_CORE' is just a mux and no need to be critical, being critical
will cause its parent clock always ON which does NOT make sense,
to make sure CPU's hardware clock source NOT being disabled during
clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent
operations to after critical clock 'ARM_CLK' setup finished.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e20703f0

drivers/clk/imx/clk-imx8mm.c

+4 −4
Original line number Diff line number Diff line
@@ -440,7 +440,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE];



	/* CORE SEL */

	hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels), CLK_IS_CRITICAL);

	hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));



	/* BUS */

	hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi",  imx8mm_main_axi_sels, base + 0x8800);
@@ -608,15 +608,15 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);

	hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL);



	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);

	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);



	hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",

					   hws[IMX8MM_CLK_A53_CORE]->clk,

					   hws[IMX8MM_CLK_A53_CORE]->clk,

					   hws[IMX8MM_ARM_PLL_OUT]->clk,

					   hws[IMX8MM_CLK_A53_DIV]->clk);



	clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);

	clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);



	imx_check_clk_hws(hws, IMX8MM_CLK_END);



	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);

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