Commit 81a6b601 authored Sep 11, 2019 by Eugen Hristev Committed by Stephen Boyd Sep 17, 2019

clk: at91: allow 24 Mhz clock as input for PLL

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 69a6bcde

drivers/clk/at91/sama5d2.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
		};

		static const struct clk_pll_characteristics plla_characteristics = {
		.input = { .min = 12000000, .max = 12000000 },
		.input = { .min = 12000000, .max = 24000000 },
		.num_output = ARRAY_SIZE(plla_outputs),
		.output = plla_outputs,
		.icpll = plla_icpll,