Commit 819779a9 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

arm64: dts: imx8mn: Add CPU thermal zone support



i.MX8MN shares same thermal sensor with i.MX8MM, add thermal zone
support for i.MX8MN.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 11699fd5
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+44 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

#include "imx8mn-pinfunc.h"

@@ -67,6 +68,7 @@
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_1: cpu@1 {
@@ -79,6 +81,7 @@
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
@@ -91,6 +94,7 @@
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
@@ -103,6 +107,7 @@
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
@@ -186,6 +191,38 @@
		method = "smc";
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
@@ -274,6 +311,13 @@
				gpio-ranges = <&iomuxc 0 119 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
				reg = <0x30260000 0x10000>;
				clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
				#thermal-sensor-cells = <0>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;