Commit 8193d9ae authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux into next/drivers 

Pull "Reset controller changes for v4.15" from Philipp Zabel:

- add ARC AX10x support,
  merged from a separate branch that is also included in the ARC tree
- add Stratix10 support via socfpga
- unify socfpga, stm32, sunxi, and zx2967 into simple-reset driver
- add Meson GX reset level control and remove an unneeded check
- add Uniphier PXs3 and ethernet reset controls
- add MT7622 reset control dt-bindings header

* tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux:
  reset: zx2967: use the reset-simple driver
  reset: stm32: use the reset-simple driver
  reset: socfpga: use the reset-simple driver
  reset: sunxi: use reset-simple driver
  reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967
  reset: meson: remove unneeded check in meson_reset_reset
  reset: meson: add level reset support for GX SoC family
  reset: uniphier: add PXs3 reset data
  reset: mediatek: add reset controller dt-bindings required header for MT7622 SoC
  reset: socfpga: build the reset-socfpga for Stratix10 SOC
  reset: uniphier: add ethernet reset control support
  reset: socfpga: fix for 64-bit compilation
  ARC: reset: introduce AXS10x reset driver
parents d5bd8507 542befbb

Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt

0 → 100644
+33 −0
Original line number Diff line number Diff line 
Binding for the AXS10x reset controller



This binding describes the ARC AXS10x boards custom IP-block which allows

to control reset signals of selected peripherals. For example DW GMAC, etc...

This block is controlled via memory-mapped register (AKA CREG) which

represents up-to 32 reset lines.



As of today only the following lines are used:

 - DW GMAC - line 5



This binding uses the common reset binding[1].



[1] Documentation/devicetree/bindings/reset/reset.txt



Required properties:

- compatible: should be "snps,axs10x-reset".

- reg: should always contain pair address - length: for creg reset

  bits register.

- #reset-cells: from common reset binding; Should always be set to 1.



Example:

	reset: reset-controller@11220 {

		compatible = "snps,axs10x-reset";

		#reset-cells = <1>;

		reg = <0x11220 0x4>;

	};



Specifying reset lines connected to IP modules:

	ethernet@.... {

		....

		resets = <&reset 5>;

		....

	};

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+3 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required properties: 
    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-reset" - for LD11 SoC

    "socionext,uniphier-ld20-reset" - for LD20 SoC

    "socionext,uniphier-pxs3-reset" - for PXs3 SoC

- #reset-cells: should be 1.



Example:
@@ -44,6 +45,7 @@ Required properties: 
    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)

    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC

    "socionext,uniphier-pxs3-sd-reset"  - for PXs3 SoC

- #reset-cells: should be 1.



Example:
@@ -74,6 +76,7 @@ Required properties: 
    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC

    "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC

- #reset-cells: should be 1.



Example:

MAINTAINERS

+6 −1
Original line number Diff line number Diff line
@@ -2136,7 +2136,6 @@ F: drivers/gpio/gpio-zx.c 
F:	drivers/i2c/busses/i2c-zx2967.c

F:	drivers/mmc/host/dw_mmc-zx.*

F:	drivers/pinctrl/zte/

F:	drivers/reset/reset-zx2967.c

F:	drivers/soc/zte/

F:	drivers/thermal/zx2967_thermal.c

F:	drivers/watchdog/zx2967_wdt.c
@@ -12914,6 +12913,12 @@ F: arch/arc/plat-axs10x 
F:	arch/arc/boot/dts/ax*

F:	Documentation/devicetree/bindings/arc/axs10*



SYNOPSYS AXS10x RESET CONTROLLER DRIVER

M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

S:	Supported

F:	drivers/reset/reset-axs10x.c

F:	Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt



SYNOPSYS DESIGNWARE DMAC DRIVER

M:	Viresh Kumar <vireshk@kernel.org>

M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

drivers/reset/Kconfig

+15 −15
Original line number Diff line number Diff line
@@ -28,6 +28,12 @@ config RESET_ATH79 
	  This enables the ATH79 reset controller driver that supports the

	  AR71xx SoC reset controller.



config RESET_AXS10X

	bool "AXS10x Reset Driver" if COMPILE_TEST

	default ARC_PLAT_AXS10X

	help

	  This enables the reset controller driver for AXS10x.



config RESET_BERLIN

	bool "Berlin Reset Driver" if COMPILE_TEST

	default ARCH_BERLIN
@@ -75,21 +81,21 @@ config RESET_PISTACHIO 
	help

	  This enables the reset driver for ImgTec Pistachio SoCs.



config RESET_SOCFPGA

	bool "SoCFPGA Reset Driver" if COMPILE_TEST

	default ARCH_SOCFPGA

config RESET_SIMPLE

	bool "Simple Reset Controller Driver" if COMPILE_TEST

	default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX

	help

	  This enables the reset controller driver for Altera SoCFPGAs.

	  This enables a simple reset controller driver for reset lines that

	  that can be asserted and deasserted by toggling bits in a contiguous,

	  exclusive register space.



config RESET_STM32

	bool "STM32 Reset Driver" if COMPILE_TEST

	default ARCH_STM32

	help

	  This enables the RCC reset controller driver for STM32 MCUs.

	  Currently this driver supports Altera SoCFPGAs, the RCC reset

	  controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family.



config RESET_SUNXI

	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI

	default ARCH_SUNXI

	select RESET_SIMPLE

	help

	  This enables the reset driver for Allwinner SoCs.
@@ -121,12 +127,6 @@ config RESET_UNIPHIER 
	  Say Y if you want to control reset signals provided by System Control

	  block, Media I/O block, Peripheral Block.



config RESET_ZX2967

	bool "ZTE ZX2967 Reset Driver"

	depends on ARCH_ZX || COMPILE_TEST

	help

	  This enables the reset controller driver for ZTE's zx2967 family.



config RESET_ZYNQ

	bool "ZYNQ Reset Driver" if COMPILE_TEST

	default ARCH_ZYNQ

drivers/reset/Makefile

+2 −3
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/ 
obj-$(CONFIG_ARCH_TEGRA) += tegra/

obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o

obj-$(CONFIG_RESET_ATH79) += reset-ath79.o

obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o

obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o

obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o

obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
@@ -12,12 +13,10 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o 
obj-$(CONFIG_RESET_MESON) += reset-meson.o

obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o

obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o

obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

obj-$(CONFIG_RESET_STM32) += reset-stm32.o

obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o

obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o

obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o

obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o

obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o

obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o

CRA Git | Maintained and supported by SUSTech CRA and CCSE