Merge tag 'usb-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next

- interrupts: Should contain phy interrupt

- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series

Optional properties:

- fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable

  high-speed trimming resistor connected in parallel with the 45 ohm resistor

  that terminates the DN output signal. Default: 45

- fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable

  high-speed trimming resistor connected in parallel with the 45 ohm resistor

  that terminates the DP output signal. Default: 45

- fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of

  the 17.78mA TX reference current. Default: 100

Example:

usbphy1: usbphy@020c9000 {

	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";

- g-use-dma: enable dma usage in gadget driver.

- g-rx-fifo-size: size of rx fifo size in gadget mode.

- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.

- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.

Deprecated properties:

- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0)

  in gadget mode.

Example:

Cavium SuperSpeed DWC3 USB SoC controller

Required properties:

- compatible:	Should contain "cavium,octeon-7130-usb-uctl"

Required child node:

A child node must exist to represent the core DWC3 IP block. The name of

the node is not important. The content of the node is defined in dwc3.txt.

Example device node:

		    uctl@1180069000000 {

			    compatible = "cavium,octeon-7130-usb-uctl";

			    reg = <0x00011800 0x69000000 0x00000000 0x00000100>;

			    ranges;

			    #address-cells = <0x00000002>;

			    #size-cells = <0x00000002>;

			    refclk-frequency = <0x05f5e100>;

			    refclk-type-ss = "dlmc_ref_clk0";

			    refclk-type-hs = "dlmc_ref_clk0";

			    power = <0x00000002 0x00000002 0x00000001>;

			    xhci@1690000000000 {

				    compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3";

				    reg = <0x00016900 0x00000000 0x00000010 0x00000000>;

				    interrupt-parent = <0x00000010>;

				    interrupts = <0x00000009 0x00000004>;

			    };

		    };

   in the array is expected to be a handle to the USB2/HS PHY and

   the second element is expected to be a handle to the USB3/SS PHY

 - phys: from the *Generic PHY* bindings

 - phy-names: from the *Generic PHY* bindings

 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"

	or "usb3-phy".

 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable

 - snps,disable_scramble_quirk: true when SW should disable data scrambling.

	Only really useful for FPGA builds.

			disabling the suspend signal to the PHY.

 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection

			in PHY P3 power state.

 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists

			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide

			a free-running PHY clock.

 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power

			from P0 to P1/P2/P3 without delay.

 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal

			utmi_l1_suspend_n, false when asserts utmi_sleep_n

 - snps,hird-threshold: HIRD threshold

			"peripheral" and "otg". In case this attribute isn't

			passed via DT, USB DRD controllers should default to

			OTG.

 - phy_type: tells USB controllers that we want to configure the core to support

			a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is

			selected. Valid arguments are "utmi" and "utmi_wide".

			In case this isn't passed via DT, USB controllers should

			default to HW capability.

 - otg-rev: tells usb driver the release number of the OTG and EH supplement

			with which the device and its descriptors are compliant,

			in binary-coded decimal (i.e. 2.0 is 0200H). This

	usb-phy = <&usb2_phy>, <&usb3,phy>;

	maximum-speed = "super-speed";

	dr_mode = "otg";

	phy_type = "utmi_wide";

	otg-rev = <0x0200>;

	adp-disable;

};