Commit 8100a580 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2020-12-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:
 "A set of fixes for x86:

   - Make the AMD L3 QoS code and data priorization enable/disable
     mechanism work correctly.

     The control bit was only set/cleared on one of the CPUs in a L3
     domain, but it has to be modified on all CPUs in the domain. The
     initial documentation was not clear about this, but the updated one
     from Oct 2020 spells it out.

   - Fix an off by one in the UV platform detection code which causes
     the UV hubs to be identified wrongly.

     The chip revisions start at 1 not at 0.

   - Fix a long standing bug in the evaluation of prefixes in the
     uprobes code which fails to handle repeated prefixes properly.

     The aggregate size of the prefixes can be larger than the bytes
     array but the code blindly iterated over the aggregate size beyond
     the array boundary. Add a macro to handle this case properly and
     use it at the affected places"

* tag 'x86-urgent-2020-12-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/sev-es: Use new for_each_insn_prefix() macro to loop over prefixes bytes
  x86/insn-eval: Use new for_each_insn_prefix() macro to loop over prefixes bytes
  x86/uprobes: Do not use prefixes.nbytes when looping over prefixes.bytes
  x86/platform/uv: Fix UV4 hub revision adjustment
  x86/resctrl: Fix AMD L3 QOS CDP enable/disable
parents 9f6b28d4 84da009f

arch/x86/boot/compressed/sev-es.c

+2 −3
Original line number Diff line number Diff line
@@ -32,13 +32,12 @@ struct ghcb *boot_ghcb; 
 */

static bool insn_has_rep_prefix(struct insn *insn)

{

	insn_byte_t p;

	int i;



	insn_get_prefixes(insn);



	for (i = 0; i < insn->prefixes.nbytes; i++) {

		insn_byte_t p = insn->prefixes.bytes[i];



	for_each_insn_prefix(insn, i, p) {

		if (p == 0xf2 || p == 0xf3)

			return true;

	}

arch/x86/include/asm/insn.h

+15 −0
Original line number Diff line number Diff line
@@ -201,6 +201,21 @@ static inline int insn_offset_immediate(struct insn *insn) 
	return insn_offset_displacement(insn) + insn->displacement.nbytes;

}



/**

 * for_each_insn_prefix() -- Iterate prefixes in the instruction

 * @insn: Pointer to struct insn.

 * @idx:  Index storage.

 * @prefix: Prefix byte.

 *

 * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix

 * and the index is stored in @idx (note that this @idx is just for a cursor,

 * do not change it.)

 * Since prefixes.nbytes can be bigger than 4 if some prefixes

 * are repeated, it cannot be used for looping over the prefixes.

 */

#define for_each_insn_prefix(insn, idx, prefix)	\

	for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)



#define POP_SS_OPCODE 0x1f

#define MOV_SREG_OPCODE 0x8e

arch/x86/kernel/apic/x2apic_uv_x.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static int __init early_set_hub_type(void) 
	/* UV4/4A only have a revision difference */

	case UV4_HUB_PART_NUMBER:

		uv_min_hub_revision_id = node_id.s.revision

					 + UV4_HUB_REVISION_BASE;

					 + UV4_HUB_REVISION_BASE - 1;

		uv_hub_type_set(UV4);

		if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)

			uv_hub_type_set(UV4|UV4A);

arch/x86/kernel/cpu/resctrl/core.c

+4 −0
Original line number Diff line number Diff line
@@ -570,6 +570,8 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r) 


	if (d) {

		cpumask_set_cpu(cpu, &d->cpu_mask);

		if (r->cache.arch_has_per_cpu_cfg)

			rdt_domain_reconfigure_cdp(r);

		return;

	}
@@ -923,6 +925,7 @@ static __init void rdt_init_res_defs_intel(void) 
		    r->rid == RDT_RESOURCE_L2CODE) {

			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

			r->cache.arch_has_per_cpu_cfg = false;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			r->msr_base = MSR_IA32_MBA_THRTL_BASE;

			r->msr_update = mba_wrmsr_intel;
@@ -943,6 +946,7 @@ static __init void rdt_init_res_defs_amd(void) 
		    r->rid == RDT_RESOURCE_L2CODE) {

			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

			r->cache.arch_has_per_cpu_cfg = true;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			r->msr_base = MSR_IA32_MBA_BW_BASE;

			r->msr_update = mba_wrmsr_amd;

arch/x86/kernel/cpu/resctrl/internal.h

+3 −0
Original line number Diff line number Diff line
@@ -360,6 +360,8 @@ struct msr_param { 
 *			executing entities

 * @arch_has_sparse_bitmaps:	True if a bitmap like f00f is valid.

 * @arch_has_empty_bitmaps:	True if the '0' bitmap is valid.

 * @arch_has_per_cpu_cfg:	True if QOS_CFG register for this cache

 *				level has CPU scope.

 */

struct rdt_cache {

	unsigned int	cbm_len;
@@ -369,6 +371,7 @@ struct rdt_cache { 
	unsigned int	shareable_bits;

	bool		arch_has_sparse_bitmaps;

	bool		arch_has_empty_bitmaps;

	bool		arch_has_per_cpu_cfg;

};



/**

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