Commit 80e4e561 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/bti-user' into for-next/bti 

Merge in user support for Branch Target Identification, which narrowly
missed the cut for 5.7 after a late ABI concern.

* for-next/bti-user:
  arm64: bti: Document behaviour for dynamically linked binaries
  arm64: elf: Fix allnoconfig kernel build with !ARCH_USE_GNU_PROPERTY
  arm64: BTI: Add Kconfig entry for userspace BTI
  mm: smaps: Report arm64 guarded pages in smaps
  arm64: mm: Display guarded pages in ptdump
  KVM: arm64: BTI: Reset BTYPE when skipping emulated instructions
  arm64: BTI: Reset BTYPE when skipping emulated instructions
  arm64: traps: Shuffle code to eliminate forward declarations
  arm64: unify native/compat instruction skipping
  arm64: BTI: Decode BYTPE bits when printing PSTATE
  arm64: elf: Enable BTI at exec based on ELF program properties
  elf: Allow arch to tweak initial mmap prot flags
  arm64: Basic Branch Target Identification support
  ELF: Add ELF program property parsing support
  ELF: UAPI and Kconfig additions for ELF program properties
parents 6a8b55ed 5d1b631c

Documentation/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -176,6 +176,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | SSBS                         | [7-4]   |    y    |

     +------------------------------+---------+---------+

     | BT                           | [3-0]   |    y    |

     +------------------------------+---------+---------+





  4) MIDR_EL1 - Main ID Register

Documentation/arm64/elf_hwcaps.rst

+5 −0
Original line number Diff line number Diff line
@@ -236,6 +236,11 @@ HWCAP2_RNG 


    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.



HWCAP2_BTI



    Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001.





4. Unused AT_HWCAP bits

-----------------------

Documentation/filesystems/proc.rst

+1 −0
Original line number Diff line number Diff line
@@ -543,6 +543,7 @@ encoded manner. The codes are the following: 
    hg    huge page advise flag

    nh    no huge page advise flag

    mg    mergable advise flag

    bt  - arm64 BTI guarded page

    ==    =======================================



Note that there is no guarantee that every flag and associated mnemonic will

arch/arm64/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ config ARM64 
	select ACPI_MCFG if (ACPI && PCI)

	select ACPI_SPCR_TABLE if ACPI

	select ACPI_PPTT if ACPI

	select ARCH_BINFMT_ELF_STATE

	select ARCH_HAS_DEBUG_VIRTUAL

	select ARCH_HAS_DEVMEM_IS_ALLOWED

	select ARCH_HAS_DMA_PREP_COHERENT
@@ -32,6 +33,7 @@ config ARM64 
	select ARCH_HAS_SYSCALL_WRAPPER

	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT

	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST

	select ARCH_HAVE_ELF_PROT

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	select ARCH_INLINE_READ_LOCK if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
@@ -61,6 +63,7 @@ config ARM64 
	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION

	select ARCH_KEEP_MEMBLOCK

	select ARCH_USE_CMPXCHG_LOCKREF

	select ARCH_USE_GNU_PROPERTY

	select ARCH_USE_QUEUED_RWLOCKS

	select ARCH_USE_QUEUED_SPINLOCKS

	select ARCH_SUPPORTS_MEMORY_FAILURE
@@ -1584,6 +1587,28 @@ endmenu 


menu "ARMv8.5 architectural features"



config ARM64_BTI

	bool "Branch Target Identification support"

	default y

	help

	  Branch Target Identification (part of the ARMv8.5 Extensions)

	  provides a mechanism to limit the set of locations to which computed

	  branch instructions such as BR or BLR can jump.



	  To make use of BTI on CPUs that support it, say Y.



	  BTI is intended to provide complementary protection to other control

	  flow integrity protection mechanisms, such as the Pointer

	  authentication mechanism provided as part of the ARMv8.3 Extensions.

	  For this reason, it does not make sense to enable this option without

	  also enabling support for pointer authentication.  Thus, when

	  enabling this option you should also select ARM64_PTR_AUTH=y.



	  Userspace binaries must also be specifically compiled to make use of

	  this mechanism.  If you say N here or the hardware does not support

	  BTI, such binaries can still run, but you get no additional

	  enforcement of branch destinations.



config ARM64_E0PD

	bool "Enable support for E0PD"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -61,7 +61,8 @@ 
#define ARM64_HAS_AMU_EXTN			51

#define ARM64_HAS_ADDRESS_AUTH			52

#define ARM64_HAS_GENERIC_AUTH			53

#define ARM64_BTI				54



#define ARM64_NCAPS				54

#define ARM64_NCAPS				55



#endif /* __ASM_CPUCAPS_H */

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