drm/amd/display: call set csc_default if enable adjustment is false (807fc072) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -1360,7 +1360,7 @@ void dpp1_cm_set_output_csc_adjustment(

		void dpp1_cm_set_output_csc_default(
		struct dpp *dpp_base,
		const struct default_adjustment *default_adjust);
		enum dc_color_space colorspace);

		void dpp1_cm_set_gamut_remap(
		struct dpp *dpp,

+2 −4

Original line number	Diff line number	Diff line
		@@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap(

		void dpp1_cm_set_output_csc_default(
		struct dpp *dpp_base,
		const struct default_adjustment *default_adjust)
		enum dc_color_space colorspace)
		{

		struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
		uint32_t ocsc_mode = 0;

		if (default_adjust != NULL) {
		switch (default_adjust->out_color_space) {
		switch (colorspace) {
		case COLOR_SPACE_SRGB:
		case COLOR_SPACE_2020_RGB_FULLRANGE:
		ocsc_mode = 0;
		@@ -254,7 +253,6 @@ void dpp1_cm_set_output_csc_default(
		default:
		break;
		}
		}

		REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);

+2 −0

Original line number	Diff line number	Diff line
		@@ -2097,6 +2097,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
		tbl_entry.color_space = color_space;
		//tbl_entry.regval = matrix;
		pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
		} else {
		pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
		}
		}
		static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

+1 −1

Original line number	Diff line number	Diff line
		@@ -64,7 +64,7 @@ struct dpp_funcs {

		void (*opp_set_csc_default)(
		struct dpp *dpp,
		const struct default_adjustment *default_adjust);
		enum dc_color_space colorspace);

		void (*opp_set_csc_adjustment)(
		struct dpp *dpp,