drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns (805cb75c) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+3 −8

Original line number	Diff line number	Diff line
		@@ -71,7 +71,6 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
		static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
		{
		uint64_t value;
		uint32_t tmp;

		/* Disable AGP. */
		WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
		@@ -98,10 +97,8 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
		(u32)((u64)adev->dummy_page.addr >> 44));

		tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
		WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
		ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
		}

		static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
		@@ -278,9 +275,7 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
		WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

		/* Setup L2 cache */
		tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
		WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
		WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
		WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
		}