Commit 8052ff43 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2020-09-04' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



A few fixes for a potential RPTR corruption issue.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGvnr6Nhz2J0sjv2G+j7iceVtaDiJDT8T88uW6jiBfOGKQ@mail.gmail.com
parents f4d51dff f6828e0c

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+5 −0
Original line number Diff line number Diff line
@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* NOTE: PM4/micro-engine firmware registers look to be the same

	 * for a2xx and a3xx.. we could possibly push that part down to

	 * adreno_gpu base class.  Or push both PM4 and PFP but

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+10 −0
Original line number Diff line number Diff line
@@ -211,6 +211,16 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	/*

	 * Use the default ringbuffer size and block size but disable the RPTR

	 * shadow

	 */

	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	/* Set the ringbuffer address */

	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* setup access protection: */

	gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+10 −0
Original line number Diff line number Diff line
@@ -267,6 +267,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	/*

	 * Use the default ringbuffer size and block size but disable the RPTR

	 * shadow

	 */

	gpu_write(gpu, REG_A4XX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	/* Set the ringbuffer address */

	gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* Load PM4: */

	ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);

	len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+11 −3
Original line number Diff line number Diff line
@@ -703,8 +703,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	a5xx_preempt_hw_init(gpu);



	if (!adreno_is_a510(adreno_gpu))

		a5xx_gpmu_ucode_init(gpu);
@@ -712,6 +710,15 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	/* Set the ringbuffer address */

	gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,

		gpu->rb[0]->iova);



	gpu_write(gpu, REG_A5XX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	a5xx_preempt_hw_init(gpu);



	/* Disable the interrupts through the initial bringup stage */

	gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
@@ -1511,7 +1518,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 


	check_speed_bin(&pdev->dev);



	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4);

	/* Restricting nr_rings to 1 to temporarily disable preemption */

	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);

	if (ret) {

		a5xx_destroy(&(a5xx_gpu->base.base));

		return ERR_PTR(ret);

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ struct a5xx_gpu { 
	struct msm_ringbuffer *next_ring;



	struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];

	struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS];

	struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS];

	uint64_t preempt_iova[MSM_GPU_MAX_RINGS];

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