Commit 804a8924 authored by Hanks Chen's avatar Hanks Chen Committed by Stephen Boyd
Browse files

clk: mediatek: add UART0 clock support 



Add MT6779 UART0 clock support.

Fixes: 710774e0 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: default avatarWendell Lin <wendell.lin@mediatek.com>
Signed-off-by: default avatarHanks Chen <hanks.chen@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9123e3a7

drivers/clk/mediatek/clk-mt6779.c

+2 −0
Original line number Diff line number Diff line
@@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { 
		    "pwm_sel", 19),

	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",

		    "pwm_sel", 21),

	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",

		    "uart_sel", 22),

	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",

		    "uart_sel", 23),

	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",

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