pinctrl: rockchip: create irq mapping in gpio_to_irq (8045ec42) · Commits · 戴 / test

drivers/pinctrl/pinctrl-rockchip.c

+12 −16

Original line number	Diff line number	Diff line
		@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)

		irq = __ffs(pend);
		pend &= ~BIT(irq);
		virq = irq_linear_revmap(bank->domain, irq);
		virq = irq_find_mapping(bank->domain, irq);

		if (!virq) {
		dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
		@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
		unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
		struct irq_chip_generic *gc;
		int ret;
		int i, j;
		int i;

		for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
		if (!bank->valid) {
		@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,

		ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
		"rockchip_gpio_irq", handle_level_irq,
		clr, 0, IRQ_GC_INIT_MASK_CACHE);
		clr, 0, 0);
		if (ret) {
		dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
		bank->name);
		@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
		continue;
		}

		/*
		* Linux assumes that all interrupts start out disabled/masked.
		* Our driver only uses the concept of masked and always keeps
		* things enabled, so for us that's all masked and all enabled.
		*/
		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);

		gc = irq_get_domain_generic_chip(bank->domain, 0);
		gc->reg_base = bank->reg_base;
		gc->private = bank;
		@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
		gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
		gc->wake_enabled = IRQ_MSK(bank->nr_pins);

		/*
		* Linux assumes that all interrupts start out disabled/masked.
		* Our driver only uses the concept of masked and always keeps
		* things enabled, so for us that's all masked and all enabled.
		*/
		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
		gc->mask_cache = 0xffffffff;

		irq_set_chained_handler_and_data(bank->irq,
		rockchip_irq_demux, bank);

		/* map the gpio irqs here, when the clock is still running */
		for (j = 0 ; j < 32 ; j++)
		irq_create_mapping(bank->domain, j);

		clk_disable(bank->clk);
		}

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