drm/amd/powerplay: fix pre-check condition for setting clock range (80381d40) · Commits · 戴 / test

This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse dpm clock layout and a zero frequency dpm level as following case. cat pp_dpm_mclk 0: 1200Mhz 1: 1200Mhz 2: 800Mhz 3: 0Mhz Signed-off-by:

Prike Liang <Prike.Liang@amd.com> Reviewed-by:

Evan Quan <evan.quan@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
		{
		int ret = 0;

		if (min <= 0 && max <= 0)
		if (min < 0 && max < 0)
		return -EINVAL;

		if (!smu_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/powerplay/smu_v12_0.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
		{
		int ret = 0;

		if (max < min)
		return -EINVAL;

		switch (clk_type) {
		case SMU_GFXCLK:
		case SMU_SCLK:

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