Commit 802a5820 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() 



Pull the code to do the CS timestamp ns<->ticks conversion into
helpers and use them all over.

The check in i915_perf_noa_delay_set() seems a bit dubious,
so we switch it to do what I assume it wanted to do all along
(ie. make sure the resulting delay in CS timestamp ticks
doesn't exceed 32bits)?

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 56f1b31f

drivers/gpu/drm/i915/i915_debugfs.c

+1 −2
Original line number Diff line number Diff line
@@ -1404,13 +1404,12 @@ static int 
i915_perf_noa_delay_set(void *data, u64 val)

{

	struct drm_i915_private *i915 = data;

	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;



	/*

	 * This would lead to infinite waits as we're doing timestamp

	 * difference on the CS with only 32bits.

	 */

	if (val > mul_u32_u32(U32_MAX, clk))

	if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)

		return -EINVAL;



	atomic64_set(&i915->perf.noa_programming_delay, val);

drivers/gpu/drm/i915/i915_drv.h

+12 −0
Original line number Diff line number Diff line
@@ -1921,4 +1921,16 @@ i915_coherent_map_type(struct drm_i915_private *i915) 
	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;

}



static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)

{

	return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,

				1000000000);

}



static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)

{

	return div_u64(val * 1000000000,

		       RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);

}



#endif

drivers/gpu/drm/i915/i915_perf.c

+2 −5
Original line number Diff line number Diff line
@@ -1612,9 +1612,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	struct drm_i915_gem_object *bo;

	struct i915_vma *vma;

	const u64 delay_ticks = 0xffffffffffffffff -

		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *

				 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,

				 1000000000);

		i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay));

	const u32 base = stream->engine->mmio_base;

#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)

	u32 *batch, *ts0, *cs, *jump;
@@ -3484,8 +3482,7 @@ err: 


static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)

{

	return div_u64(1000000000 * (2ULL << exponent),

		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);

	return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent);

}



/**

drivers/gpu/drm/i915/intel_device_info.c

+1 −1
Original line number Diff line number Diff line
@@ -1052,7 +1052,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
		read_timestamp_frequency(dev_priv);

	if (runtime->cs_timestamp_frequency_hz) {

		runtime->cs_timestamp_period_ns =

			div_u64(1e9, runtime->cs_timestamp_frequency_hz);

			i915_cs_timestamp_ticks_to_ns(dev_priv, 1);

		drm_dbg(&dev_priv->drm,

			"CS timestamp wraparound in %lldms\n",

			div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,

drivers/gpu/drm/i915/selftests/i915_perf.c

+1 −2
Original line number Diff line number Diff line
@@ -262,8 +262,7 @@ static int live_noa_delay(void *arg) 


	delay = intel_read_status_page(stream->engine, 0x102);

	delay -= intel_read_status_page(stream->engine, 0x100);

	delay = div_u64(mul_u32_u32(delay, 1000000000),

			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);

	delay = i915_cs_timestamp_ticks_to_ns(i915, delay);

	pr_info("GPU delay: %uns, expected %lluns\n",

		delay, expected);

CRA Git | Maintained and supported by SUSTech CRA and CCSE